Inventor · disambiguated record
Tobias Gemmeke
Also filed as: GEMMEKE TOBIAS
19 granted patents·5 pending applications·85 citations·filing 2006–2017
92Inventor score
Top patents by PatentIndex Score
24 records- 0190US8860502B2Method and apparatus for monitoring timing of critical pathsSTICHTING IMEC NEDERLAND·Filed 2013·Granted Oct 14, 2014·19 cites·15 claims
- 0284US7509511B1Reducing register file leakage current within a processorIBM·Filed 2008·Granted Mar 24, 2009·14 cites·1 claims
- 0383US7502918B1Method and system for data dependent performance increment and power reductionIBM·Filed 2008·Granted Mar 10, 2009·13 cites·1 claims
- 0482US7890901B2Method and system for verifying the equivalence of digital circuitsIBM·Filed 2007·Granted Feb 15, 2011·12 cites·15 claims
- 0577US9477419B2Memory control system for a non-volatile memory and control methodSTICHTING IMEC NEDERLAND·Filed 2014·Granted Oct 25, 2016·5 cites·16 claims
- 0674US7849428B2Formally deriving a minimal clock-gating schemeIBM·Filed 2008·Granted Dec 7, 2010·7 cites·20 claims
- 0772US7996738B2Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chipIBM·Filed 2008·Granted Aug 9, 2011·7 cites·20 claims
- 0865US7624363B2Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemesIBM·Filed 2007·Granted Nov 24, 2009·3 cites·5 claims
- 0960US8312069B2Permute unit and method to operate a permute unitGEMMEKE TOBIAS·Filed 2007·Granted Nov 13, 2012·2 cites·9 claims
- 1051US8756263B2Binary logic unit and method to operate a binary logic unitIBM·Filed 2013·Granted Jun 17, 2014·0 cites·5 claims
- 1151US7735038B2Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuitIBM·Filed 2007·Granted Jun 8, 2010·1 cites·7 claims
- 1251US7639046B2Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuitIBM·Filed 2007·Granted Dec 29, 2009·1 cites·12 claims
- 1350US7913132B2System and method for scanning sequential logic elementsIBM·Filed 2008·Granted Mar 22, 2011·1 cites·14 claims
- 1448US8452824B2Binary logic unit and method to operate a binary logic unitGEMMEKE TOBIAS·Filed 2007·Granted May 28, 2013·0 cites·4 claims
- 1547US8370409B2Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processingIBM·Filed 2008·Granted Feb 5, 2013·0 cites·7 claims
- 1647US8266411B2Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importanceGEMMEKE TOBIAS·Filed 2009·Granted Sep 11, 2012·0 cites·12 claims
- 1747US2009249035A1Multi-cycle register file bypassIBM·Filed 2008·Application pending·0 cites
- 1846US7962538B2Method of operand width reduction to enable usage of narrower saturation adderIBM·Filed 2006·Granted Jun 14, 2011·0 cites·15 claims
- 1944US2007165343A1Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a CircuitBAROWSKI HARRY·Filed 2006·Application pending·0 cites
- 2042US2018165395A1Computer-implemented method for generating an advanced-on-chip-variation table of a cell and a non-transitory computer readable medium for doing the sameSTICHTING IMEC NEDERLAND·Filed 2017·Application pending·0 cites
- 2139US9425795B2Circuit and method for detection and compensation of transistor mismatchSTICHTING IMEC NEDERLAND·Filed 2014·Granted Aug 23, 2016·0 cites·17 claims
- 2238US7795914B2Circuit design methodology to reduce leakage powerIBM·Filed 2008·Granted Sep 14, 2010·0 cites·4 claims
- 2337US2007168792A1Method to Reduce Leakage Within a Sequential Network and Latch CircuitIBM·Filed 2006·Application pending·0 cites
- 2431US2016161979A1Process Skew Resilient Digital CMOS CircuitSTICHTING IMEC NEDERLAND·Filed 2015·Application pending·0 cites
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