Inventor · disambiguated record
Le Trong Nguyen
Also filed as: NGUYEN LE · NGUYEN LE T · NGUYEN LE TRONG
101 granted patents·3 pending applications·5,597 citations·filing 1983–2019
99Inventor score
Top patents by PatentIndex Score
104 records- 0196US6611908B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2001·Granted Aug 26, 2003·83 cites·12 claims
- 0296US6058465ASingle-instruction-multiple-data processing in a multimedia signal processorFiled 1996·Granted May 2, 2000·255 cites·14 claims
- 0396US5978838ACoordination and synchronization of an asymmetric, single-chip, dual multiprocessorSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Nov 2, 1999·264 cites·15 claims
- 0496US5440752AMicroprocessor architecture with a switch network for data transfer between cache, memory port, and IOUSEIKO EPSON CORP·Filed 1991·Granted Aug 8, 1995·170 cites·35 claims
- 0595US7739482B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2006·Granted Jun 15, 2010·26 cites·18 claims
- 0695US6425054B1Multiprocessor operation in a multimedia signal processorSAMSUNG ELECTRONICS CO LTD·Filed 2000·Granted Jul 23, 2002·120 cites·10 claims
- 0795US5560032AHigh-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·193 cites·29 claims
- 0895US5539911AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1992·Granted Jul 23, 1996·133 cites·56 claims
- 0995US5438668ASystem and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computerSEIKO EPSON CORP·Filed 1992·Granted Aug 1, 1995·159 cites·29 claims
- 1094US5838984ASingle-instruction-multiple-data processing using multiple banks of vector registersSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Nov 17, 1998·245 cites·13 claims
- 1193US5497499ASuperscalar risc instruction schedulingSEIKO EPSON CORP·Filed 1994·Granted Mar 5, 1996·120 cites·16 claims
- 1292US6647485B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2001·Granted Nov 11, 2003·42 cites·40 claims
- 1392US6272579B1Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·120 cites·8 claims
- 1492US6061711AEfficient context saving and restoring in a multi-tasking computing system environmentSAMSUNG ELECTRONICS INC·Filed 1996·Granted May 9, 2000·218 cites·23 claims
- 1591US5689720AHigh-performance superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1996·Granted Nov 18, 1997·90 cites·11 claims
- 1691US5493687ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1991·Granted Feb 20, 1996·103 cites·5 claims
- 1790US6965987B2System and method for handling load and/or store operations in a superscalar microprocessorSEIKO EPSON CORP·Filed 2003·Granted Nov 15, 2005·43 cites·58 claims
- 1890US5619666ASystem for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processorSEIKO EPSON CORP·Filed 1995·Granted Apr 8, 1997·110 cites·12 claims
- 1990US5560035ARISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 1995·Granted Sep 24, 1996·105 cites·8 claims
- 2089US6986024B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jan 10, 2006·28 cites·24 claims
- 2188US6954844B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2003·Granted Oct 11, 2005·29 cites·23 claims
- 2288US6915412B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Jul 5, 2005·25 cites·26 claims
- 2388US5860158ACache control unit with a cache request transaction-oriented protocolSAMSUNG ELECTRONICS CO LTD·Filed 1996·Granted Jan 12, 1999·158 cites·37 claims
- 2488US5754800AMulti processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruptionSEIKO EPSON CORP·Filed 1995·Granted May 19, 1998·86 cites·6 claims
- 2587US7685402B2RISC microprocessor architecture implementing multiple typed register setsGARG SANJIV·Filed 2007·Granted Mar 23, 2010·10 cites·12 claims
- 2687US7657712B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2005·Granted Feb 2, 2010·10 cites·12 claims
- 2787US6948052B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Sep 20, 2005·23 cites·39 claims
- 2887US5961629AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1998·Granted Oct 5, 1999·135 cites·27 claims
- 2987US5546552AMethod for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processorSEIKO EPSON CORP·Filed 1995·Granted Aug 13, 1996·82 cites·7 claims
- 3086US7721070B2High-performance, superscalar-based computer system with out-of-order instruction executionNGUYEN LE TRONG·Filed 2008·Granted May 18, 2010·10 cites·21 claims
- 3186US7162610B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Jan 9, 2007·21 cites·35 claims
- 3285US7051187B2Superscalar RISC instruction schedulingTRANSMETA CORP·Filed 2002·Granted May 23, 2006·24 cites·19 claims
- 3385US6959375B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2002·Granted Oct 25, 2005·19 cites·10 claims
- 3484US7174525B2Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2004·Granted Feb 6, 2007·21 cites·8 claims
- 3584US6934829B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Aug 23, 2005·17 cites·21 claims
- 3684US6782521B2Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2002·Granted Aug 24, 2004·21 cites·7 claims
- 3784US6249856B1RISC microprocessor architecture implementing multiple typed register setsSEIKO EPSON CORP·Filed 2000·Granted Jun 19, 2001·26 cites·17 claims
- 3884US5371684ASemiconductor floor plan for a register renaming circuitSEIKO EPSON CORP·Filed 1992·Granted Dec 6, 1994·63 cites·1 claims
- 3982US6401232B1Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chipSEIKO EPSON CORP·Filed 2000·Granted Jun 4, 2002·19 cites·5 claims
- 4082US5448705ARISC microprocessor architecture implementing fast trap and exception stateSEIKO EPSON CORP·Filed 1993·Granted Sep 5, 1995·79 cites·3 claims
- 4181US7664935B2System and method for translating non-native instructions to native instructions for processing on a host processorCOON BRETT·Filed 2008·Granted Feb 16, 2010·6 cites·18 claims
- 4281US6219763B1System and method for adjusting priorities associated with multiple devices seeking access to a memory array unitSEIKO EPSON CORP·Filed 1999·Granted Apr 17, 2001·55 cites·4 claims
- 4381US5961628ALoad and store unit for a vector processorSAMSUNG ELECTRONICS CO LTD·Filed 1997·Granted Oct 5, 1999·112 cites·23 claims
- 4480US7555632B2High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2005·Granted Jun 30, 2009·6 cites·23 claims
- 4580US6941447B2High-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 2003·Granted Sep 6, 2005·13 cites·23 claims
- 4680US6128723AHigh-performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Oct 3, 2000·42 cites·27 claims
- 4779US7941635B2High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2006·Granted May 10, 2011·5 cites·5 claims
- 4879US7028161B2High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distributionSEIKO EPSON CORP·Filed 2001·Granted Apr 11, 2006·17 cites·39 claims
- 4979US6401194B1Execution unit for processing a data stream independently and in parallelSAMSUNG ELECTRONICS CO LTD·Filed 1997·Granted Jun 4, 2002·92 cites·22 claims
- 5079US6038654AHigh performance, superscalar-based computer system with out-of-order instruction executionSEIKO EPSON CORP·Filed 1999·Granted Mar 14, 2000·39 cites·80 claims
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