Inventor · disambiguated record
Charles P. Roth
Also filed as: ROTH CHARLES · ROTH CHARLES P · ROTH CHARLES PHILIP
63 granted patents·1 pending application·2,347 citations·filing 1995–2019
99Inventor score
Top patents by PatentIndex Score
64 records- 0199US6948056B1Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stagesANALOG DEVICES INC·Filed 2000·Granted Sep 20, 2005·422 cites·4 claims
- 0290US7028165B2Processor stallingANALOG DEVICES INC·Filed 2000·Granted Apr 11, 2006·66 cites·30 claims
- 0390US6823448B2Exception handling using an exception pipeline in a pipelined processorINTEL CORP·Filed 2000·Granted Nov 23, 2004·69 cites·25 claims
- 0488US6754808B1Valid bit generation and tracking in a pipelined processorINTEL CORP·Filed 2000·Granted Jun 22, 2004·51 cites·26 claims
- 0585US5691920AMethod and system for performance monitoring of dispatch unit efficiency in a processing systemIBM·Filed 1995·Granted Nov 25, 1997·122 cites·11 claims
- 0684US5937437AMethod and apparatus for monitoring address translation performanceIBM·Filed 1996·Granted Aug 10, 1999·108 cites·14 claims
- 0782US6343337B1Wide shifting in the vector permute unitIBM·Filed 2000·Granted Jan 29, 2002·32 cites·20 claims
- 0882US5797019AMethod and system for performance monitoring time lengths of disabled interrupts in a processing systemIBM·Filed 1995·Granted Aug 18, 1998·102 cites·11 claims
- 0981US5987598AMethod and system for tracking instruction progress within a data processing systemIBM·Filed 1997·Granted Nov 16, 1999·89 cites·21 claims
- 1079US5938760ASystem and method for performance monitoring of instructions in a re-order bufferIBM·Filed 1996·Granted Aug 17, 1999·83 cites·19 claims
- 1178US6986026B2Single-step processing and selecting debugging modesANALOG DEVICES INC·Filed 2000·Granted Jan 10, 2006·31 cites·8 claims
- 1278US6189072B1Performance monitoring of cache misses and instructions completed for instruction parallelism analysisIBM·Filed 1996·Granted Feb 13, 2001·84 cites·16 claims
- 1378US5875294AMethod and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal statesIBM·Filed 1995·Granted Feb 23, 1999·74 cites·24 claims
- 1478US5835702APerformance monitorIBM·Filed 1996·Granted Nov 10, 1998·80 cites·6 claims
- 1576US10216515B2Processor load using a bit vector to calculate effective addressORACLE INT CORP·Filed 2016·Granted Feb 26, 2019·2 cites·14 claims
- 1676US6134710AAdaptive method and system to minimize the effect of long cache missesIBM·Filed 1998·Granted Oct 17, 2000·71 cites·30 claims
- 1775US7272705B2Early exception detectionANALOG DEVICES INC·Filed 2005·Granted Sep 18, 2007·6 cites·12 claims
- 1875US6067644ASystem and method monitoring instruction progress within a processorIBM·Filed 1998·Granted May 23, 2000·70 cites·14 claims
- 1975US5991708APerformance monitor and method for performance monitoring within a data processing systemIBM·Filed 1997·Granted Nov 23, 1999·70 cites·24 claims
- 2075US5970439APerformance monitoring in a data processing systemIBM·Filed 1997·Granted Oct 19, 1999·71 cites·19 claims
- 2174US6748523B1Hardware loopsINTEL CORP·Filed 2000·Granted Jun 8, 2004·19 cites·43 claims
- 2273US6665795B1Resetting a programmable processorINTEL CORP·Filed 2000·Granted Dec 16, 2003·18 cites·45 claims
- 2372US10877755B2Processor load using a bit vector to calculate effective addressORACLE INT CORP·Filed 2019·Granted Dec 29, 2020·1 cites·20 claims
- 2470US6898693B1Hardware loopsANALOG DEVICES INC·Filed 2000·Granted May 24, 2005·15 cites·75 claims
- 2570US5751945AMethod and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing systemIBM·Filed 1995·Granted May 12, 1998·58 cites·25 claims
- 2668US7100033B2Controlling the timing of test modes in a multiple processor systemINTEL CORP·Filed 2002·Granted Aug 29, 2006·18 cites·15 claims
- 2767US7155570B1FIFO write/LIFO read trace buffer with software and hardware loop compressionANALOG DEVICES INC·Filed 2000·Granted Dec 26, 2006·13 cites·30 claims
- 2866US6766444B1Hardware loopsINTEL CORP·Filed 2000·Granted Jul 20, 2004·11 cites·26 claims
- 2966US6708296B1Method and system for selecting and distinguishing an event sequence using an effective address in a processing systemIBM·Filed 1995·Granted Mar 16, 2004·42 cites·28 claims
- 3066US6499116B1Performance of data stream touch eventsIBM·Filed 1999·Granted Dec 24, 2002·48 cites·39 claims
- 3165US7168032B2Data synchronization for a test access portANALOG DEVICES INC·Filed 2000·Granted Jan 23, 2007·10 cites·23 claims
- 3263US6842812B1Event handlingINTEL CORP·Filed 2000·Granted Jan 11, 2005·9 cites·27 claims
- 3362US6976151B1Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destinationANALOG DEVICES INC·Filed 2000·Granted Dec 13, 2005·8 cites·15 claims
- 3460US6920515B2Early exception detectionANALOG DEVICES INC·Filed 2001·Granted Jul 19, 2005·6 cites·12 claims
- 3560US6470440B1Vector compare and maximum/minimum generation apparatus and method thereforIBM·Filed 1999·Granted Oct 22, 2002·42 cites·23 claims
- 3659US5949971AMethod and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing systemIBM·Filed 1995·Granted Sep 7, 1999·35 cites·13 claims
- 3759US5881306AInstruction fetch bandwidth analysisIBM·Filed 1996·Granted Mar 9, 1999·34 cites·18 claims
- 3858US7360059B2Variable width alignment engine for aligning instructions based on transition between buffersANALOG DEVICES INC·Filed 2006·Granted Apr 15, 2008·1 cites·18 claims
- 3957US6789184B1Instruction address generation and tracking in a pipelined processorINTEL CORP·Filed 2000·Granted Sep 7, 2004·5 cites·20 claims
- 4056US6249906B1Adaptive method and system to minimize the effect of long table walksIBM·Filed 1998·Granted Jun 19, 2001·30 cites·28 claims
- 4155US7082516B1Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanismANALOG DEVICES INC·Filed 2000·Granted Jul 25, 2006·4 cites·12 claims
- 4255US7069420B1Decode and dispatch of multi-issue and multiple width instructionsANALOG DEVICES INC·Filed 2000·Granted Jun 27, 2006·4 cites·18 claims
- 4355US7065636B2Hardware loops and pipeline system using advanced generation of loop parametersANALOG DEVICES INC·Filed 2000·Granted Jun 20, 2006·4 cites·29 claims
- 4455US6728870B1Register move operationsINTEL CORP·Filed 2000·Granted Apr 27, 2004·4 cites·13 claims
- 4555US6327651B1Wide shifting in the vector permute unitIBM·Filed 1998·Granted Dec 4, 2001·25 cites·21 claims
- 4654US6829701B2Watchpoint engine for a pipelined processorINTEL CORP·Filed 2000·Granted Dec 7, 2004·4 cites·8 claims
- 4753US7366876B1Efficient emulation instruction dispatch based on instruction widthANALOG DEVICES INC·Filed 2000·Granted Apr 29, 2008·3 cites·23 claims
- 4853US6178500B1Vector packing and saturation detection in the vector permute unitIBM·Filed 1998·Granted Jan 23, 2001·25 cites·18 claims
- 4952US7043582B2Self-nesting interruptsANALOG DEVICES INC·Filed 2002·Granted May 9, 2006·2 cites·27 claims
- 5052US6760800B1Event vector table overrideINTEL CORP·Filed 2000·Granted Jul 6, 2004·2 cites·27 claims
Showing the top 50 of 64 patent records by PatentIndex Score.
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