Inventor · disambiguated record
Gary W. Thome
Also filed as: THOME GARY · THOME GARY W · THOME GARY WILLIAM
49 granted patents·1 pending application·1,776 citations·filing 1989–2015
99Inventor score
Files withCOMPAQ COMPUTER CORP46ADVANCED MICRO DEVICES INC1HEWLETT PACKARD DEVELOPMENT CO1HEWLETT PACKARD ENTPR DEV LP1LEIGH KEVIN B1
Top patents by PatentIndex Score
50 records- 0187US5537555AFully pipelined and highly concurrent memory controllerCOMPAQ COMPUTER CORP·Filed 1993·Granted Jul 16, 1996·128 cites·9 claims
- 0287US5524235ASystem for arbitrating access to memory with dynamic priority assignmentCOMPAQ COMPUTER CORP·Filed 1994·Granted Jun 4, 1996·127 cites·24 claims
- 0384US5991865AMPEG motion compensation using operand routing and performing add and divide in a single instructionCOMPAQ COMPUTER CORP·Filed 1996·Granted Nov 23, 1999·121 cites·12 claims
- 0480US5892964AComputer bridge interfaces for accelerated graphics port and peripheral component interconnect devicesCOMPAQ COMPUTER CORP·Filed 1997·Granted Apr 6, 1999·98 cites·19 claims
- 0578US5289584AMemory system with FIFO data inputCOMPAQ COMPUTER CORP·Filed 1991·Granted Feb 22, 1994·81 cites·16 claims
- 0677US6154831ADecoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific valuesADVANCED MICRO DEVICES INC·Filed 1999·Granted Nov 28, 2000·66 cites·21 claims
- 0776US5651130AMemory controller that dynamically predicts page missesCOMPAQ COMPUTER CORP·Filed 1995·Granted Jul 22, 1997·41 cites·18 claims
- 0876US5509138AMethod for determining speeds of memory modulesCOMPAQ COMPUTER CORP·Filed 1993·Granted Apr 16, 1996·81 cites·6 claims
- 0976US5440751ABurst data transfer to single cycle data transfer conversion and strobe signal conversionCOMPAQ COMPUTER CORP·Filed 1991·Granted Aug 8, 1995·73 cites·4 claims
- 1075US5634073ASystem having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operationCOMPAQ COMPUTER CORP·Filed 1994·Granted May 27, 1997·53 cites·2 claims
- 1173US5893145ASystem and method for routing operands within partitions of a source register to partitions within a destination registerCOMPAQ COMPUTER CORP·Filed 1996·Granted Apr 6, 1999·66 cites·20 claims
- 1272US6009505ASystem and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slotCOMPAQ COMPUTER CORP·Filed 1996·Granted Dec 28, 1999·57 cites·11 claims
- 1371US5652856AMemory controller having all DRAM address and control singals provided synchronously from a single deviceCOMPAQ COMPUTER CORP·Filed 1996·Granted Jul 29, 1997·55 cites·11 claims
- 1469US9003091B2Flow control for a Serial Peripheral Interface busHEWLETT PACKARD DEVELOPMENT CO·Filed 2012·Granted Apr 7, 2015·2 cites·19 claims
- 1567US5586286AMemory controller having flip-flops for synchronously generating DRAM address and control signals from a single chipCOMPAQ COMPUTER CORP·Filed 1995·Granted Dec 17, 1996·47 cites·7 claims
- 1666US5778413AProgrammable memory controller having two level look-up for memory timing parameterCOMPAQ COMPUTER CORP·Filed 1996·Granted Jul 7, 1998·49 cites·55 claims
- 1766US5353423AMemory controller for use with write-back cache system and multiple bus masters coupled to multiple busesCOMPAQ COMPUTER CORP·Filed 1991·Granted Oct 4, 1994·50 cites·3 claims
- 1865US5862063AEnhanced wavetable processing technique on a vector processor having operand routing and slot selectable operationsCOMPAQ COMPUTER CORP·Filed 1996·Granted Jan 19, 1999·25 cites·18 claims
- 1965US5819105ASystem in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering deviceCOMPAQ COMPUTER CORP·Filed 1995·Granted Oct 6, 1998·36 cites·26 claims
- 2064US5581727AHierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence controlCOMPAQ COMPUTER CORP·Filed 1993·Granted Dec 3, 1996·31 cites·5 claims
- 2164US5475829AComputer system which overrides write protection status during execution in system management modeCOMPAQ COMPUTER CORP·Filed 1993·Granted Dec 12, 1995·34 cites·5 claims
- 2263US5931892AEnhanced adaptive filtering techniqueCOMPAQ COMPUTER CORP·Filed 1996·Granted Aug 3, 1999·18 cites·22 claims
- 2359US6061521AComputer having multimedia operations executable as two distinct sets of operations within a single instruction cycleCOMPAQ COMPUTER CORP·Filed 1996·Granted May 9, 2000·30 cites·11 claims
- 2459US5813038AMemory controller having precharge prediction based on processor and PC bus cyclesCOMPAQ COMPUTER CORP·Filed 1997·Granted Sep 22, 1998·28 cites·26 claims
- 2557US5938739AMemory controller including write posting queues, bus read control logic, and a data contents counterCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 17, 1999·25 cites·26 claims
- 2657US5408636ASystem for flushing first and second caches upon detection of a write operation to write protected areasCOMPAQ COMPUTER CORP·Filed 1994·Granted Apr 18, 1995·30 cites·4 claims
- 2756US5918023ASystem design to support either Pentium Pro processors, Pentium II processors, and future processor without having to replace the system boardCOMPAQ COMPUTER CORP·Filed 1997·Granted Jun 29, 1999·38 cites·19 claims
- 2855US5960459AMemory controller having precharge prediction based on processor and PCI bus cyclesCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 28, 1999·22 cites·20 claims
- 2954US5809549ABurst SRAMs for use with a high speed clockCOMPAQ COMPUTER CORP·Filed 1997·Granted Sep 15, 1998·13 cites·24 claims
- 3053US6115791AHierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence controlCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 5, 2000·20 cites·24 claims
- 3153US5634112AMemory controller having precharge prediction based on processor and PCI bus cyclesCOMPAQ COMPUTER CORP·Filed 1994·Granted May 27, 1997·19 cites·27 claims
- 3252US5640532AMicroprocessor cache memory way prediction based on the way of previous memory readCOMPAQ COMPUTER CORP·Filed 1994·Granted Jun 17, 1997·21 cites·5 claims
- 3352US5604884ABurst SRAMS for use with a high speed clockCOMPAQ COMPUTER CORP·Filed 1993·Granted Feb 18, 1997·20 cites·1 claims
- 3452US5454081AExpansion bus type determination apparatusCOMPAQ COMPUTER CORP·Filed 1992·Granted Sep 26, 1995·24 cites·13 claims
- 3550US5579512ASystempro emulation in a symmetric multiprocessing computer systemCOMPAQ COMPUTER CORP·Filed 1994·Granted Nov 26, 1996·20 cites·4 claims
- 3649US5509139ACircuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management modeCOMPAQ COMPUTER CORP·Filed 1993·Granted Apr 16, 1996·20 cites·10 claims
- 3749US5210847ANoncacheable address random access memoryCOMPAQ COMPUTER CORP·Filed 1989·Granted May 11, 1993·17 cites·12 claims
- 3844US5596741AComputer system which overrides write protection status during execution in system management modeCOMPAQ COMPUTER CORP·Filed 1995·Granted Jan 21, 1997·14 cites·10 claims
- 3942US6215504B1Line drawing using operand routing and operation selective multimedia extension unitCOMPAQ COMPUTER CORP·Filed 1997·Granted Apr 10, 2001·12 cites·11 claims
- 4039US5822756AMicroprocessor cache memory way prediction based on the way of a previous memory readCOMPAQ COMPUTER CORP·Filed 1997·Granted Oct 13, 1998·10 cites·33 claims
- 4139US5404559AApparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycleCOMPAQ COMPUTER CORP·Filed 1993·Granted Apr 4, 1995·10 cites·7 claims
- 4239US2014314417A1Reconfiguration of an optical connection infrastructureLEIGH KEVIN B·Filed 2012·Application pending·0 cites
- 4338US5778433AComputer system including a first level write-back cache and a second level cacheCOMPAQ COMPUTER CORP·Filed 1996·Granted Jul 7, 1998·8 cites·12 claims
- 4437US5692154ACircuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memoryCOMPAQ COMPUTER CORP·Filed 1996·Granted Nov 25, 1997·11 cites·8 claims
- 4536US5325535ALock signal extension and interruption apparatusCOMPAQ COMPUTER CORP·Filed 1991·Granted Jun 28, 1994·7 cites·9 claims
- 4635US11100000B2Embedded image managementHEWLETT PACKARD ENTPR DEV LP·Filed 2015·Granted Aug 24, 2021·0 cites·19 claims
- 4733US5857116ACircuit for disabling an address masking control signal when a microprocessor is in a system management modeCOMPAQ COMPUTER CORP·Filed 1997·Granted Jan 5, 1999·8 cites·15 claims
- 4832US5848267AComputer system speed control using memory refresh counterCOMPAQ COMPUTER CORP·Filed 1997·Granted Dec 8, 1998·3 cites·17 claims
- 4930US5664225ACircuit for disabling an address masking control signal when a microprocessor is in a system management modeCOMPAQ COMPUTER CORP·Filed 1995·Granted Sep 2, 1997·4 cites·24 claims
- 5030US5423021AAuxiliary control signal decode using high performance address linesCOMPAQ COMPUTER CORP·Filed 1993·Granted Jun 6, 1995·3 cites·4 claims
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