Inventor · disambiguated record
Jing-Ye Juang
Also filed as: JUANG JING-YE
7 granted patents·6 pending applications·18 citations·filing 2009–2025
76Inventor score
Technology areasH10W
Files withTAIWAN SEMICONDUCTOR MFG CO LTD8IND TECH RES INST2NATIONAL YANG MING CHIAO TUNG UNIV2LU SU-TSAI1
Top patents by PatentIndex Score
13 records- 0189US12387945B2Semiconductor structures including glass core layer and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 12, 2025·1 cites·20 claims
- 0288US9184153B2Chip stack structure and method for fabricating the sameLU SU-TSAI·Filed 2012·Granted Nov 10, 2015·15 cites·16 claims
- 0383US11145619B2Electrical connecting structure having nano-twins copper and method of forming the sameNATIONAL YANG MING CHIAO TUNG UNIV·Filed 2020·Granted Oct 12, 2021·2 cites·12 claims
- 0479US2025364343A1Reinforced structure with capping layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0576US2025336685A1Semiconductor structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0674US2024387338A1Reconstructed substrates for high i/o counts application and methods for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0774US2025300048A1Dual-underfill encapsulation for packaging and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0870US12489043B2Reconstructed substrates for high I/O counts application and methods for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 0970US12347758B2Dual-underfill encapsulation for packaging and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 1, 2025·0 cites·20 claims
- 1064US2023395450A1Reinforced structure with capping layer and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Application pending·0 cites
- 1162US11715721B2Electrical connecting structure having nano-twins copperNATIONAL YANG MING CHIAO TUNG UNIV·Filed 2021·Granted Aug 1, 2023·0 cites·7 claims
- 1245US2010207266A1Chip package structureIND TECH RES INST·Filed 2009·Application pending·0 cites
- 1340US8384215B2Wafer level molding structureIND TECH RES INST·Filed 2010·Granted Feb 26, 2013·0 cites·26 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →