Inventor

CHOQUETTE JACK

US41 patents

⚠️ This page may combine multiple inventors who share the name “CHOQUETTE JACK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOQUETTE JACK

NVIDIA CORP

Managing data sparsity for neural networks

Robust, efficient multiprocessor-coprocessor interface

Techniques for efficiently transferring data to a processor

Techniques for comprehensively synchronizing execution threads

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Programmatically controlled data multicasting across multiple compute engines

High performance synchronization mechanisms for coordinating operations on a computer system

Unified cache for diverse memory traffic

Techniques for maintaining atomicity and ordering for pixel shader operations

Techniques for maintaining atomicity and ordering for pixel shader operations

Techniques for maintaining atomicity and ordering for pixel shader operations

Binding constants at runtime for improved resource utilization

Robust, efficient multiprocessor-coprocessor interface

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Robust, efficient multiprocessor-coprocessor interface

Techniques for efficiently transferring data to a processor

Techniques for efficiently transferring data to a processor

Unified cache for diverse memory traffic

Simultaneous compute and graphics scheduling

Cooperative group arrays

Distributed shared memory

Convergence among concurrently executing threads

Convergence among concurrently executing threads

Scalarization of instructions for SIMT architectures

Thread-level sleep in a multithreaded architecture

Techniques for maintaining atomicity and ordering for pixel shader operations

Techniques for comprehensively synchronizing execution threads

Unified cache for diverse memory traffic

Hardware accelerated synchronization with asynchronous transaction support

Uniform register file for improved resource utilization

RAZA MICROELECTRONICS INC

Method and system for reducing taken branch penalty

Method for coordinating information flow between components

Method for providing a synchronous communication and transaction between functions on an integrated circuit therefore the functions operate independently at their own optimized speeds

Method and system for initiating computation upon unordered receipt of data

AZUL SYSTEMS INC

Ordering operation

Processor instruction used to determine whether to perform a memory-related trap

SANDCRAFT INC

Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units

Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units

TENE GIL

Instruction based interrupt masking for managing interrupts in a computer environment

SHEBANOW MICHAEL C

Trap handler architecture for a parallel processing unit

CHOQUETTE JACK

Method and system for resolving thread divergences