Inventor · disambiguated record
Robertus Laurentius Van Der Valk
Also filed as: VALK ROBERTUS LAURENTIUS VAN D · VAN DER VALK ROBERTUS · VAN DER VALK ROBERTUS L · VAN DER VALK ROBERTUS LAURENTI
16 granted patents·1 pending application·210 citations·filing 1996–2014
93Inventor score
Top patents by PatentIndex Score
17 records- 0189US7369002B2Phase locked loop fast lock methodZARLINK SEMICONDUCTOR INC·Filed 2006·Granted May 6, 2008·28 cites·16 claims
- 0288US7315546B2Alignment of clock domains in packet networksZARLINK SEMICONDUCTOR INC·Filed 2004·Granted Jan 1, 2008·32 cites·26 claims
- 0380US7078946B2Analog PLL with switched capacitor resampling filterZARLINK SEMICONDUCTOR INC·Filed 2002·Granted Jul 18, 2006·31 cites·16 claims
- 0477US7356036B2Method providing distribution means for reference clocks across packetized networksZARLINK SEMICONDUCTOR INC·Filed 2004·Granted Apr 8, 2008·14 cites·10 claims
- 0575US7738501B2Method of recovering timing over a granular packet networkZARLINK SEMICONDUCTOR INC·Filed 2006·Granted Jun 15, 2010·7 cites·18 claims
- 0670US7642862B2Digital phase locked loopZARLINK SEMICONDUCTOR INC·Filed 2007·Granted Jan 5, 2010·9 cites·2 claims
- 0769US6784706B2Method of stabilizing phase-locked loopZARLINK SEMICONDUCTOR INC·Filed 2002·Granted Aug 31, 2004·18 cites·14 claims
- 0868US7728634B2Flexible waveform generator with extended range capabilityZARLINK SEMICONDUCTOR INC·Filed 2008·Granted Jun 1, 2010·4 cites·20 claims
- 0964US7557624B2Fractional digital PLLZARLINK SEMICONDUCTOR INC·Filed 2007·Granted Jul 7, 2009·6 cites·17 claims
- 1062US8907706B2Phase locked loop with simultaneous locking to low and high frequency clocksMICROSEMI SEMICONDUCTOR ULC·Filed 2014·Granted Dec 9, 2014·2 cites·18 claims
- 1162US6795520B2High speed digital countersZARLINK SEMICONDUCTOR INC·Filed 2003·Granted Sep 21, 2004·10 cites·18 claims
- 1261US5905388AFrequency synthesizerX INTEGRATED CIRCUITS BV·Filed 1996·Granted May 18, 1999·35 cites·12 claims
- 1360US7619483B2Asynchronous phase acquisition unit with ditheringZARLINK SEMICONDUCTOR INC·Filed 2007·Granted Nov 17, 2009·5 cites·6 claims
- 1457US7376156B2Alignment of clocks over multiple packet networksZARLINK SEMICONDUCTOR INC·Filed 2004·Granted May 20, 2008·4 cites·5 claims
- 1552US7096243B2Flexible decimatorZARLINK SEMICONDUCTOR INC·Filed 2003·Granted Aug 22, 2006·5 cites·19 claims
- 1641US7385990B2Method to improve the resolution of time measurements and alignment in packet networks by time modulationZARLINK SEMICONDUCTOR INC·Filed 2003·Granted Jun 10, 2008·0 cites·18 claims
- 1739US2004153894A1Method of measuring the accuracy of a clock signalZARLINK SEMICONDUCTOR INC·Filed 2003·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →