Inventor · disambiguated record
James O. Nicholson
Also filed as: NICHOLSON JAMES · NICHOLSON JAMES O · NICHOLSON JAMES OTTO
21 granted patents·854 citations·filing 1989–2012
96Inventor score
Top patents by PatentIndex Score
21 records- 0194US5251303ASystem for DMA block data transfer based on linked control blocksIBM·Filed 1989·Granted Oct 5, 1993·210 cites·8 claims
- 0287US6807232B2System and method for multiplexing synchronous digital data streamsNAT INSTR CORP·Filed 2000·Granted Oct 19, 2004·40 cites·26 claims
- 0381US5701495AScalable system interrupt structure for a multi-processing systemIBM·Filed 1995·Granted Dec 23, 1997·105 cites·25 claims
- 0477US5090014AIdentifying likely failure points in a digital data processing systemDIGITAL EQUIPMENT CORP·Filed 1989·Granted Feb 18, 1992·63 cites·20 claims
- 0573US6134621AVariable slot configuration for multi-speed busIBM·Filed 1998·Granted Oct 17, 2000·63 cites·17 claims
- 0672US5237676AHigh speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected deviceIBM·Filed 1989·Granted Aug 17, 1993·46 cites·5 claims
- 0769US5109490AData transfer using bus address linesIBM·Filed 1989·Granted Apr 28, 1992·41 cites·1 claims
- 0866US5469463AExpert system for identifying likely failure points in a digital data processing systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted Nov 21, 1995·53 cites·51 claims
- 0965US5506972AComputer system having dynamically programmable linear/fairness priority arbitration schemeIBM·Filed 1994·Granted Apr 9, 1996·41 cites·14 claims
- 1061US9626243B2Data error correction device and methods thereofNICHOLSON JAMES O·Filed 2009·Granted Apr 18, 2017·3 cites·20 claims
- 1156US5287457AComputer system DMA transferIBM·Filed 1992·Granted Feb 15, 1994·31 cites·10 claims
- 1254US5388228AComputer system having dynamically programmable linear/fairness priority arbitration schemeIBM·Filed 1993·Granted Feb 7, 1995·25 cites·2 claims
- 1353US8199695B2Clock signal synchronization among computers in a networkDE ARAUJO DANIEL N·Filed 2007·Granted Jun 12, 2012·1 cites·18 claims
- 1453US6223299B1Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enablesIBM·Filed 1998·Granted Apr 24, 2001·26 cites·28 claims
- 1553US5418927AI/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the linesIBM·Filed 1992·Granted May 23, 1995·27 cites·7 claims
- 1648US5274784AData transfer using bus address linesIBM·Filed 1991·Granted Dec 28, 1993·20 cites·25 claims
- 1747US5293622AComputer system with input/output cacheIBM·Filed 1992·Granted Mar 8, 1994·17 cites·5 claims
- 1845US5287482AInput/output cacheIBM·Filed 1992·Granted Feb 15, 1994·17 cites·7 claims
- 1944US9306694B2Clock signal synchronization among computers in a networkDE ARAUJO DANIEL N·Filed 2012·Granted Apr 5, 2016·0 cites·19 claims
- 2039US5161219AComputer system with input/output cacheIBM·Filed 1991·Granted Nov 3, 1992·10 cites·3 claims
- 2138US6226720B1Method for optimally configuring memory in a mixed interleave systemIBM·Filed 1998·Granted May 1, 2001·15 cites·12 claims
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