Inventor · disambiguated record
G. Glenn Henry
Also filed as: HENRY G G · HENRY G GLENN
379 granted patents·28 pending applications·3,695 citations·filing 1997–2018
99Inventor score
Files withVIA TECH INC108VIA ALLIANCE SEMICONDUCTOR CO LTD99IP FIRST LLC93HENRY G GLENN69INTEGRATED DEVICE TECH9
Top patents by PatentIndex Score
407 records- 0198US8879345B1Microprocessor mechanism for decompression of fuse correction dataVIA TECH INC·Filed 2013·Granted Nov 4, 2014·71 cites·21 claims
- 0297US8978132B2Apparatus and method for managing a microprocessor providing for a secure execution modeHENRY G GLENN·Filed 2008·Granted Mar 10, 2015·41 cites·24 claims
- 0397US8242800B2Apparatus and method for override access to a secured programmable fuse arrayHENRY G GLENN·Filed 2010·Granted Aug 14, 2012·29 cites·24 claims
- 0496US10430706B2Processor with memory array operable as either last level cache slice or neural network unit memoryVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 1, 2019·26 cites·18 claims
- 0596US8982655B1Apparatus and method for compression and decompression of microprocessor configuration dataVIA TECH INC·Filed 2013·Granted Mar 17, 2015·30 cites·18 claims
- 0696US6571331B2Static branch prediction mechanism for conditional branch instructionsIP FIRST LLC·Filed 2001·Granted May 27, 2003·112 cites·8 claims
- 0795US10417560B2Neural network unit that performs efficient 3-dimensional convolutionsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Sep 17, 2019·22 cites·31 claims
- 0895US9509336B1Hardware data compressor that pre-huffman encodes to decide whether to huffman encode a matched string or a back pointer theretoVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Nov 29, 2016·16 cites·17 claims
- 0995US9389863B2Processor that performs approximate computing instructionsVIA TECH INC·Filed 2014·Granted Jul 12, 2016·30 cites·25 claims
- 1095US8370641B2Initialization of a microprocessor providing for execution of secure codeVIA TECH INC·Filed 2008·Granted Feb 5, 2013·26 cites·27 claims
- 1194US10438115B2Neural network unit with memory layout to perform efficient 3-dimensional convolutionsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 8, 2019·21 cites·21 claims
- 1294US10387366B2Neural network unit with shared activation function unitsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Aug 20, 2019·9 cites·21 claims
- 1393US10664751B2Processor with memory array operable as either cache memory or neural network unit memoryVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted May 26, 2020·11 cites·10 claims
- 1493US10586148B2Neural network unit with re-shapeable memoryVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Mar 10, 2020·15 cites·21 claims
- 1593US10366050B2Multi-operation neural network unitVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Jul 30, 2019·7 cites·22 claims
- 1693US10353862B2Neural network unit that performs stochastic roundingVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Jul 16, 2019·8 cites·21 claims
- 1793US9043580B2Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)HENRY G GLENN·Filed 2012·Granted May 26, 2015·21 cites·18 claims
- 1893US8615799B2Microprocessor having secure non-volatile storage accessHENRY G GLENN·Filed 2008·Granted Dec 24, 2013·17 cites·22 claims
- 1993US8255703B2Atomic hash instructionCRISPIN THOMAS A·Filed 2011·Granted Aug 28, 2012·18 cites·20 claims
- 2093US7707397B2Variable group associativity branch target address cache delivering multiple target addresses per cache lineVIA TECH INC·Filed 2005·Granted Apr 27, 2010·34 cites·74 claims
- 2193US7663957B2Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessorVIA TECH INC·Filed 2008·Granted Feb 16, 2010·34 cites·38 claims
- 2292US10552370B2Neural network unit with output buffer feedback for performing recurrent neural network computationsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Feb 4, 2020·5 cites·19 claims
- 2392US6647489B1Compare branch instruction pairing within a single integer pipelineIP FIRST LLC·Filed 2000·Granted Nov 11, 2003·76 cites·29 claims
- 2491US10671564B2Neural network unit that performs convolutions using collective shift register among array of neural processing unitsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Jun 2, 2020·7 cites·21 claims
- 2591US9967092B2Key expansion logic using decryption key primitivesVIA TECH INC·Filed 2015·Granted May 8, 2018·10 cites·21 claims
- 2691US7788433B2Microprocessor apparatus providing for secure interrupts and exceptionsVIA TECH INC·Filed 2008·Granted Aug 31, 2010·13 cites·27 claims
- 2791US6681311B2Translation lookaside buffer that caches memory type informationIP FIRST LLC·Filed 2001·Granted Jan 20, 2004·71 cites·35 claims
- 2890US10423876B2Processor with memory array operable as either victim cache or neural network unit memoryVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Sep 24, 2019·10 cites·19 claims
- 2990US9465432B2Multi-core synchronization mechanismVIA TECH INC·Filed 2014·Granted Oct 11, 2016·10 cites·33 claims
- 3090US8615672B2Multicore processor power credit management to allow all processing cores to operate at elevated frequencyHENRY G GLENN·Filed 2011·Granted Dec 24, 2013·8 cites·36 claims
- 3190US8392693B2Fast REP STOS using grabline operationsHENRY G GLENN·Filed 2010·Granted Mar 5, 2013·13 cites·34 claims
- 3290US8090931B2Microprocessor with fused store address/store data microinstructionCOL GERARD M·Filed 2008·Granted Jan 3, 2012·24 cites·12 claims
- 3390US6886093B2Speculative hybrid branch direction predictorIP FIRST LLC·Filed 2001·Granted Apr 26, 2005·56 cites·41 claims
- 3489US9971605B2Selective designation of multiple cores as bootstrap processor in a multi-core microprocessorVIA TECH INC·Filed 2014·Granted May 15, 2018·5 cites·18 claims
- 3589US9503122B1Hardware data compressor that sorts hash chains based on node string match probabilitiesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Nov 22, 2016·9 cites·21 claims
- 3689US8972707B2Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pinHENRY G GLENN·Filed 2011·Granted Mar 3, 2015·8 cites·12 claims
- 3789US7529912B2Apparatus and method for instruction-level specification of floating point formatVIA TECH INC·Filed 2005·Granted May 5, 2009·21 cites·28 claims
- 3889US7065632B1Method and apparatus for speculatively forwarding storehit data in a hierarchical mannerIP FIRST LLC·Filed 2000·Granted Jun 20, 2006·65 cites·15 claims
- 3988US9911008B2Microprocessor with on-the-fly switching of decryption keysVIA TECH INC·Filed 2015·Granted Mar 6, 2018·6 cites·15 claims
- 4088US9507404B2Single core wakeup multi-core synchronization mechanismVIA TECH INC·Filed 2014·Granted Nov 29, 2016·5 cites·18 claims
- 4188US8819839B2Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levelsHENRY G GLENN·Filed 2008·Granted Aug 26, 2014·19 cites·24 claims
- 4288US8793803B2Termination of secure execution mode in a microprocessor providing for execution of secure codeHENRY G GLENN·Filed 2008·Granted Jul 29, 2014·9 cites·27 claims
- 4388US6823444B1Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrapIP FIRST LLC·Filed 2001·Granted Nov 23, 2004·47 cites·11 claims
- 4488US5889679AFuse array control for smart function enableINTEGRATED DEVICE TECH·Filed 1997·Granted Mar 30, 1999·157 cites·47 claims
- 4587US9898291B2Microprocessor with arm and X86 instruction length decodersVIA TECH INC·Filed 2015·Granted Feb 20, 2018·5 cites·22 claims
- 4687US9891927B2Inter-core communication via uncore RAMVIA TECH INC·Filed 2014·Granted Feb 13, 2018·4 cites·19 claims
- 4787US9628111B2Hardware data compressor with multiple string match search hash tables each based on different hash sizeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Apr 18, 2017·7 cites·19 claims
- 4887US9535488B2Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processorVIA TECH INC·Filed 2014·Granted Jan 3, 2017·4 cites·31 claims
- 4987US9244686B2Microprocessor that translates conditional load/store instructions into variable number of microinstructionsHENRY G GLENN·Filed 2012·Granted Jan 26, 2016·10 cites·47 claims
- 5087US7917568B2X87 fused multiply-add instructionVIA TECH INC·Filed 2007·Granted Mar 29, 2011·16 cites·15 claims
Showing the top 50 of 407 patent records by PatentIndex Score.
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