Inventor · disambiguated record
Prabhakar P. Tripathi
Also filed as: TRIPATHI PRABHAKAR P · TRIPATHI PRABHAKAR PATI
9 granted patents·167 citations·filing 1991–2003
89Inventor score
Files withLSI LOGIC CORP9
Top patents by PatentIndex Score
9 records- 0178US6109775AMethod for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereonLSI LOGIC CORP·Filed 1997·Granted Aug 29, 2000·60 cites·18 claims
- 0274US5776831AMethod of forming a high electromigration resistant metallization systemLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·36 cites·18 claims
- 0370US6664141B1Method of forming metal fuses in CMOS processes with copper interconnectLSI LOGIC CORP·Filed 2001·Granted Dec 16, 2003·14 cites·21 claims
- 0468US6828653B1Method of forming metal fuses in CMOS processes with copper interconnectLSI LOGIC CORP·Filed 2003·Granted Dec 7, 2004·12 cites·6 claims
- 0566US6569751B1Low via resistance systemLSI LOGIC CORP·Filed 2000·Granted May 27, 2003·9 cites·17 claims
- 0648US5477466AMethod and structure for improving patterning design for processingLSI LOGIC CORP·Filed 1994·Granted Dec 19, 1995·13 cites·18 claims
- 0748US5379233AMethod and structure for improving patterning design for processingLSI LOGIC CORP·Filed 1991·Granted Jan 3, 1995·13 cites·13 claims
- 0845US5654897AMethod and structure for improving patterning design for processingLSI LOGIC CORP·Filed 1995·Granted Aug 5, 1997·10 cites·29 claims
- 0942US6893962B2Low via resistance systemLSI LOGIC CORP·Filed 2003·Granted May 17, 2005·0 cites·3 claims
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