Inventor · disambiguated record
Cheng-Long Tang
Also filed as: TANG CHENG-LONG
13 granted patents·719 citations·filing 1991–2005
95Inventor score
Technology areasG06F
Files withSEIKO EPSON CORP13
Top patents by PatentIndex Score
13 records- 0196US6611908B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2001·Granted Aug 26, 2003·83 cites·12 claims
- 0296US5440752AMicroprocessor architecture with a switch network for data transfer between cache, memory port, and IOUSEIKO EPSON CORP·Filed 1991·Granted Aug 8, 1995·170 cites·35 claims
- 0392US6272579B1Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 1999·Granted Aug 7, 2001·120 cites·8 claims
- 0488US6954844B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2003·Granted Oct 11, 2005·29 cites·23 claims
- 0588US5754800AMulti processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruptionSEIKO EPSON CORP·Filed 1995·Granted May 19, 1998·86 cites·6 claims
- 0687US7657712B2Microprocessor architecture capable of supporting multiple heterogeneous processorsSEIKO EPSON CORP·Filed 2005·Granted Feb 2, 2010·10 cites·12 claims
- 0781US6219763B1System and method for adjusting priorities associated with multiple devices seeking access to a memory array unitSEIKO EPSON CORP·Filed 1999·Granted Apr 17, 2001·55 cites·4 claims
- 0879US5604865AMicroprocessor architecture with a switch network for data transfer between cache, memory port, and IOUSEIKO EPSON CORP·Filed 1995·Granted Feb 18, 1997·50 cites·20 claims
- 0975US5941979AMicroprocessor architecture with a switch network and an arbitration unit for controlling access to memory portsSEIKO EPSON CORP·Filed 1997·Granted Aug 24, 1999·40 cites·6 claims
- 1066US6047348ASystem and method for supporting a multiple width memory subsystemSEIKO EPSON CORP·Filed 1999·Granted Apr 4, 2000·37 cites·11 claims
- 1159US5594877ASystem for transferring data onto buses having different widthsSEIKO EPSON CORP·Filed 1994·Granted Jan 14, 1997·25 cites·3 claims
- 1242US5887148ASystem for supporting a buffer memory wherein data is stored in multiple data widths based upon a switch interface for detecting the different bus sizesSEIKO EPSON CORP·Filed 1996·Granted Mar 23, 1999·11 cites·17 claims
- 1331US5828861ASystem and method for reducing the critical path in memory control unit and input/output control unit operationsSEIKO EPSON CORP·Filed 1992·Granted Oct 27, 1998·3 cites·9 claims
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