Inventor · disambiguated record
Charles F. Webb
Also filed as: WEBB CHARLES · WEBB CHARLES F · WEBB CHARLES FRANKLIN
101 granted patents·5 pending applications·1,599 citations·filing 1977–2024
99Inventor score
Top patents by PatentIndex Score
106 records- 0196US4167799ACarpet cleaning machineWEBB CHARLES F·Filed 1978·Granted Sep 18, 1979·100 cites·3 claims
- 0295US8850166B2Load pair disjoint facility and instruction thereforeJACOBI CHRISTIAN·Filed 2010·Granted Sep 30, 2014·37 cites·17 claims
- 0394US8103851B2Dynamic address translation with translation table entry format control for indentifying format of the translation table entryGREINER DAN F·Filed 2008·Granted Jan 24, 2012·30 cites·27 claims
- 0492US8117417B2Dynamic address translation with change record overrideGREINER DAN F·Filed 2008·Granted Feb 14, 2012·21 cites·21 claims
- 0591US8380907B2Method, system and computer program product for providing filtering of GUEST2 quiesce requestsIBM·Filed 2008·Granted Feb 19, 2013·25 cites·14 claims
- 0690US5461721ASystem for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs)IBM·Filed 1993·Granted Oct 24, 1995·156 cites·18 claims
- 0788US7966453B2Method and apparatus for active software disown of cache line's exlusive rightsIBM·Filed 2007·Granted Jun 21, 2011·11 cites·19 claims
- 0886US9934159B2Dynamic address translation with fetch protection in an emulated environmentIBM·Filed 2016·Granted Apr 3, 2018·3 cites·12 claims
- 0986US8037278B2Dynamic address translation with format controlIBM·Filed 2008·Granted Oct 11, 2011·15 cites·24 claims
- 1085US5504859AData processor with enhanced error recoveryIBM·Filed 1993·Granted Apr 2, 1996·118 cites·16 claims
- 1184US9311238B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2014·Granted Apr 12, 2016·4 cites·14 claims
- 1284US8631216B2Dynamic address translation with change record overrideGREINER DAN F·Filed 2012·Granted Jan 14, 2014·6 cites·15 claims
- 1384US8621180B2Dynamic address translation with translation table entry format control for identifying format of the translation table entryGREINER DAN F·Filed 2011·Granted Dec 31, 2013·6 cites·20 claims
- 1483US9250915B2Operand fetching control as a function of branch confidenceIBM·Filed 2012·Granted Feb 2, 2016·6 cites·9 claims
- 1583US8078843B2Facilitating processing in a computing environment using an extended drain instructionALEXANDER KHARY J·Filed 2008·Granted Dec 13, 2011·11 cites·18 claims
- 1682US8131982B2Branch prediction instructions having mask values involving unloading and loading branch history dataEMMA PHILIP G·Filed 2008·Granted Mar 6, 2012·12 cites·9 claims
- 1782US8019964B2Dynamic address translation with DAT protectionINTERNAT BUISNESS MACHINES CORP·Filed 2008·Granted Sep 13, 2011·14 cites·25 claims
- 1881US6119219ASystem serialization with early release of individual processorIBM·Filed 1998·Granted Sep 12, 2000·98 cites·13 claims
- 1978US9921964B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2017·Granted Mar 20, 2018·1 cites·11 claims
- 2078US9921965B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2017·Granted Mar 20, 2018·1 cites·11 claims
- 2178US8407453B2Facilitating processing in a computing environment using an extended drain instructionALEXANDER KHARY J·Filed 2011·Granted Mar 26, 2013·4 cites·18 claims
- 2278US6865645B1Program store compare handling between instruction and operand cachesIBM·Filed 2000·Granted Mar 8, 2005·27 cites·25 claims
- 2377US9244856B2Dynamic address translation with translation table entry format control for identifying format of the translation table entryIBM·Filed 2013·Granted Jan 26, 2016·3 cites·20 claims
- 2476US7953932B2System and method for avoiding deadlocks when performing storage updates in a multi-processor environmentIBM·Filed 2008·Granted May 31, 2011·7 cites·20 claims
- 2576US6079013AMultiprocessor serialization with early release of processorsIBM·Filed 1998·Granted Jun 20, 2000·76 cites·11 claims
- 2675US8862834B2Shared memory translation facilityIBM·Filed 2013·Granted Oct 14, 2014·3 cites·17 claims
- 2774US6671793B1Method and system for managing the result from a translator co-processor in a pipelined processorIBM·Filed 2000·Granted Dec 30, 2003·23 cites·11 claims
- 2871US9052889B2Load pair disjoint facility and instruction thereforIBM·Filed 2012·Granted Jun 9, 2015·2 cites·26 claims
- 2971US5495590ACheckpoint synchronization with instruction overlap enabledIBM·Filed 1995·Granted Feb 27, 1996·55 cites·6 claims
- 3069US7882338B2Method, system and computer program product for an implicit predicted return from a predicted subroutineIBM·Filed 2008·Granted Feb 1, 2011·4 cites·20 claims
- 3167US10977190B2Dynamic address translation with access control in an emulator environmentIBM·Filed 2019·Granted Apr 13, 2021·0 cites·10 claims
- 3267US5345567ASystem and method for modifying program status word system mask, system access key, and address space code with overlap enabledIBM·Filed 1991·Granted Sep 6, 1994·51 cites·21 claims
- 3366US8549255B2Microprocessor, method and computer program product for direct page prefetch in millicode capable computer systemSCHROTER DAVID A·Filed 2008·Granted Oct 1, 2013·5 cites·17 claims
- 3465US5276882ASubroutine return through branch history tableIBM·Filed 1990·Granted Jan 4, 1994·47 cites·5 claims
- 3563US9619384B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2016·Granted Apr 11, 2017·0 cites·21 claims
- 3663US8032709B2System, method and computer program product for handling shared cache lines in a multi-processor environmentIBM·Filed 2008·Granted Oct 4, 2011·2 cites·20 claims
- 3762US10423539B2Dynamic address translation with access control in an emulator environmentIBM·Filed 2017·Granted Sep 24, 2019·0 cites·20 claims
- 3862US9612969B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2016·Granted Apr 4, 2017·0 cites·21 claims
- 3962US9501416B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2016·Granted Nov 22, 2016·0 cites·7 claims
- 4062US9471503B2Demote instruction for relinquishing cache line ownershipIBM·Filed 2016·Granted Oct 18, 2016·0 cites·7 claims
- 4161US7478185B2Directly initiating by external adapters the setting of interruption initiativesIBM·Filed 2007·Granted Jan 13, 2009·2 cites·9 claims
- 4261US5257354ASystem for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct resultsIBM·Filed 1991·Granted Oct 26, 1993·38 cites·13 claims
- 4360US5802359AMapping processor state into a millicode addressable processor state register arrayIBM·Filed 1997·Granted Sep 1, 1998·38 cites·2 claims
- 4459US7971034B2Reduced overhead address mode change management in a pipelined, recycling microprocessorIBM·Filed 2008·Granted Jun 28, 2011·1 cites·1 claims
- 4558US9021225B2Dynamic address translation with fetch protection in an emulated environmentIBM·Filed 2013·Granted Apr 28, 2015·0 cites·12 claims
- 4658US5694617ASystem for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operationIBM·Filed 1995·Granted Dec 2, 1997·40 cites·3 claims
- 4757US9003134B2Emulation of a dynamic address translation with change record override on a machine of another architectureIBM·Filed 2013·Granted Apr 7, 2015·0 cites·15 claims
- 4857US8112174B2Processor, method and computer program product for fast selective invalidation of translation lookaside bufferHSIEH JONATHAN T·Filed 2008·Granted Feb 7, 2012·2 cites·19 claims
- 4957US6058470ASpecialized millicode instruction for translate and testIBM·Filed 1998·Granted May 2, 2000·33 cites·4 claims
- 5056US10970224B2Operational context subspacesIBM·Filed 2019·Granted Apr 6, 2021·0 cites·20 claims
Showing the top 50 of 106 patent records by PatentIndex Score.
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