Inventor · disambiguated record
Nitin Y. Borkar
Also filed as: BORKAR NITIN · BORKAR NITIN Y · BORKAR NITIN YESHWANT
28 granted patents·8 pending applications·648 citations·filing 1992–2024
97Inventor score
Files withINTEL CORP22NARENDRA SIVA G3QUALCOMM INTELLIGENT SOLUTIONS INC3QUALCOMM INC2RANKIN LINDA J2
Top patents by PatentIndex Score
36 records- 0196US8288846B2Power management integrated circuitNARENDRA SIVA G·Filed 2010·Granted Oct 16, 2012·23 cites·22 claims
- 0291US7058750B1Scalable distributed memory and I/O multiprocessor systemINTEL CORP·Filed 2000·Granted Jun 6, 2006·53 cites·17 claims
- 0390US9992135B2Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfacesINTEL CORP·Filed 2015·Granted Jun 5, 2018·9 cites·23 claims
- 0490US7343442B2Scalable distributed memory and I/O multiprocessor systems and associated methodsINTEL CORP·Filed 2006·Granted Mar 11, 2008·17 cites·20 claims
- 0589US5613071AMethod and apparatus for providing remote memory access in a distributed memory multiprocessor systemINTEL CORP·Filed 1995·Granted Mar 18, 1997·216 cites·12 claims
- 0688US7181544B2Network protocol engineINTEL CORP·Filed 2002·Granted Feb 20, 2007·62 cites·26 claims
- 0787US9063730B2Performing variation-aware profiling and dynamic core allocation for a many-core processorDIGHE SAURABH·Filed 2010·Granted Jun 23, 2015·13 cites·18 claims
- 0887US7930464B2Scalable memory and I/O multiprocessor systemsINTEL CORP·Filed 2009·Granted Apr 19, 2011·11 cites·7 claims
- 0982US7668165B2Hardware-based multi-threading for packet processingINTEL CORP·Filed 2004·Granted Feb 23, 2010·36 cites·19 claims
- 1081US8379659B2Performance and traffic aware heterogeneous interconnection networkINTEL CORP·Filed 2010·Granted Feb 19, 2013·6 cites·19 claims
- 1180US11093416B1Memory system supporting programmable selective access to subsets of parallel-arranged memory chips for efficient memory accessesQUALCOMM INTELLIGENT SOLUTIONS INC·Filed 2020·Granted Aug 17, 2021·2 cites·26 claims
- 1280US7603508B2Scalable distributed memory and I/O multiprocessor systems and associated methodsINTEL CORP·Filed 2008·Granted Oct 13, 2009·6 cites·38 claims
- 1379US5357512AConditional carry scheduler for round robin schedulingINTEL CORP·Filed 1992·Granted Oct 18, 1994·101 cites·8 claims
- 1478US7671456B2Power management integrated circuitINTEL CORP·Filed 2007·Granted Mar 2, 2010·6 cites·20 claims
- 1578US7247930B2Power management integrated circuitINTEL CORP·Filed 2004·Granted Jul 24, 2007·19 cites·17 claims
- 1673US8745306B2Scalable distributed memory and I/O multiprocessor systemRANKIN LINDA J·Filed 2012·Granted Jun 3, 2014·2 cites·20 claims
- 1767US7016354B2Packet-based clock signalINTEL CORP·Filed 2002·Granted Mar 21, 2006·11 cites·41 claims
- 1867US6798265B2Low jitter external clockingINTEL CORP·Filed 2002·Granted Sep 28, 2004·10 cites·9 claims
- 1964US7051295B2IC design process including automated removal of body contacts from MOSFET devicesINTEL CORP·Filed 2003·Granted May 23, 2006·10 cites·26 claims
- 2063US12360765B2Processing unit employing micro-operations (micro-ops) random access memory (RAM) as main program memoryQUALCOMM INC·Filed 2023·Granted Jul 15, 2025·0 cites·24 claims
- 2159US7698576B2CPU power delivery systemINTEL CORP·Filed 2004·Granted Apr 13, 2010·5 cites·11 claims
- 2258US7620119B2Communications receiver with digital counterINTEL CORP·Filed 2004·Granted Nov 17, 2009·5 cites·14 claims
- 2358US2025377798A1Memory modules with random access memory (ram) memory chips supporting distinct, multiple single-word memory accesses, and related memory systems and methodsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2451US8255605B2Scalable distributed memory and I/O multiprocessor systemRANKIN LINDA J·Filed 2011·Granted Aug 28, 2012·0 cites·20 claims
- 2550US11194744B2In-line memory module (IMM) computing node with an embedded processor(s) to support local processing of memory-based operations for lower latency and reduced power consumptionQUALCOMM INTELLIGENT SOLUTIONS INC·Filed 2020·Granted Dec 7, 2021·0 cites·22 claims
- 2648US11755498B2Emulating scratchpad functionality using caches in processor-based devicesQUALCOMM INTELLIGENT SOLUTIONS INC·Filed 2020·Granted Sep 12, 2023·0 cites·20 claims
- 2748US2005007163A1Low jitter external clockingINTEL CORP·Filed 2004·Application pending·0 cites
- 2847US6411151B1Low jitter external clockingINTEL CORP·Filed 1999·Granted Jun 25, 2002·15 cites·20 claims
- 2947US2015050337A1Extended Release CompositionsKUNDU SUBRATA·Filed 2013·Application pending·0 cites
- 3047US2010115301A1Cpu power delivery systemNARENDRA SIVA G·Filed 2010·Application pending·0 cites
- 3143US2004044796A1Tracking out-of-order packetsFiled 2002·Application pending·0 cites
- 3243US2005165985A1Network protocol processorFiled 2003·Application pending·0 cites
- 3342US2016170456A9Power management integrated circuitINTEL CORP·Filed 2012·Application pending·0 cites
- 3439US2006071650A1CPU power delivery systemNARENDRA SIVA G·Filed 2004·Application pending·0 cites
- 3538US6865134B2Charge recycling decoder, method, and systemINTEL CORP·Filed 2003·Granted Mar 8, 2005·1 cites·28 claims
- 3636US5930486AMethod and device for gracious arbitration of access to a computer system resourceINTEL CORP·Filed 1996·Granted Jul 27, 1999·9 cites·12 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →