Inventor · disambiguated record
Kenneth L. Ward
Also filed as: WARD KENNETH L · WARD KENNETH LUNDY
33 granted patents·1 pending application·100 citations·filing 1994–2020
95Inventor score
Files withIBM33
Top patents by PatentIndex Score
34 records- 0190US11086630B1Finish exception handling of an instruction completion tableIBM·Filed 2020·Granted Aug 10, 2021·3 cites·20 claims
- 0287US7409589B2Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processorIBM·Filed 2005·Granted Aug 5, 2008·20 cites·20 claims
- 0383US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 0483US9798549B1Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2016·Granted Oct 24, 2017·3 cites·13 claims
- 0578US10901743B2Speculative execution of both paths of a weakly predicted branch instructionIBM·Filed 2018·Granted Jan 26, 2021·2 cites·20 claims
- 0678US7487377B2Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computerIBM·Filed 2005·Granted Feb 3, 2009·7 cites·8 claims
- 0777US7865758B2Fault tolerant time synchronization mechanism in a scaleable multi-processor computerIBM·Filed 2008·Granted Jan 4, 2011·6 cites·8 claims
- 0877US7526583B2Method and apparatus to launch write queue read data in a microprocessor recovery unitIBM·Filed 2005·Granted Apr 28, 2009·8 cites·7 claims
- 0971US10761856B2Instruction completion table containing entries that share instruction tagsIBM·Filed 2018·Granted Sep 1, 2020·1 cites·17 claims
- 1069US7870406B2Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processorIBM·Filed 2005·Granted Jan 11, 2011·4 cites·21 claims
- 1167US10423423B2Efficiently managing speculative finish tracking and error handling for load instructionsIBM·Filed 2015·Granted Sep 24, 2019·1 cites·13 claims
- 1265US9971604B2History buffer for multiple-field registersIBM·Filed 2015·Granted May 15, 2018·1 cites·20 claims
- 1364US11366671B2Completion mechanism for a microprocessor instruction completion tableIBM·Filed 2020·Granted Jun 21, 2022·0 cites·20 claims
- 1464US10108423B2History buffer with single snoop tag for multiple-field registersIBM·Filed 2015·Granted Oct 23, 2018·1 cites·20 claims
- 1563US9996353B2Universal history buffer to support multiple register typesIBM·Filed 2015·Granted Jun 12, 2018·1 cites·20 claims
- 1663US5752734ARail components for pick-up or flat-bed trucks to support side or back piecesFiled 1994·Granted May 19, 1998·28 cites·7 claims
- 1761US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 1860US7761726B2Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computerIBM·Filed 2008·Granted Jul 20, 2010·1 cites·7 claims
- 1959US10725786B2Completion mechanism for a microprocessor instruction completion tableIBM·Filed 2018·Granted Jul 28, 2020·0 cites·20 claims
- 2057US7603497B2Method and apparatus to launch write queue read data in a microprocessor recovery unitIBM·Filed 2009·Granted Oct 13, 2009·2 cites·12 claims
- 2156US10929144B2Speculatively releasing store data before store instruction completion in a processorIBM·Filed 2019·Granted Feb 23, 2021·0 cites·18 claims
- 2256US10169046B2Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2017·Granted Jan 1, 2019·0 cites·12 claims
- 2354US10831489B2Mechanism for completing atomic instructions in a microprocessorIBM·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 2454US10713057B2Mechanism to stop completions using stop codes in an instruction completion tableIBM·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 2553US10877763B2Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processorIBM·Filed 2018·Granted Dec 29, 2020·0 cites·18 claims
- 2650US10977034B2Instruction completion table with ready-to-complete vectorIBM·Filed 2018·Granted Apr 13, 2021·0 cites·19 claims
- 2750US10552165B2Efficiently managing speculative finish tracking and error handling for load instructionsIBM·Filed 2015·Granted Feb 4, 2020·0 cites·7 claims
- 2847US11030018B2On-demand multi-tiered hang buster for SMT microprocessorIBM·Filed 2017·Granted Jun 8, 2021·0 cites·18 claims
- 2945US10831492B2Most favored branch issueIBM·Filed 2018·Granted Nov 10, 2020·0 cites·6 claims
- 3044US11269647B2Finish status reporting for a simultaneous multithreading processor using an instruction completion tableIBM·Filed 2017·Granted Mar 8, 2022·0 cites·20 claims
- 3143US11068274B2Prioritized instructions in an instruction completion table of a simultaneous multithreading processorIBM·Filed 2017·Granted Jul 20, 2021·0 cites·20 claims
- 3243US9971687B2Operation of a multi-slice processor with history buffers storing transaction memory state informationIBM·Filed 2016·Granted May 15, 2018·0 cites·12 claims
- 3339US2017300336A1Fpscr sticky bit handling for out of order instruction executionIBM·Filed 2016·Application pending·0 cites
- 3430US5805836AMethod and apparatus for equalizing grants of a data bus to primary and secondary devicesIBM·Filed 1996·Granted Sep 8, 1998·8 cites·12 claims
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