Inventor · disambiguated record
Nikhil Mehta
Also filed as: MEHTA NIKHIL · MEHTA NIKHIL J · MEHTA NIKHIL JASVANT
9 granted patents·18 pending applications·0 citations·filing 2019–2024
74Inventor score
Top patents by PatentIndex Score
27 records- 0175US12426247B2Capacitor connections in dielectric layersINTEL CORP·Filed 2023·Granted Sep 23, 2025·0 cites·20 claims
- 0267US11991873B2Capacitor separations in dielectric layersINTEL CORP·Filed 2023·Granted May 21, 2024·0 cites·18 claims
- 0359US2025393283A1Thin film transistors having self-aligned contact metallizationINTEL CORP·Filed 2024·Application pending·0 cites
- 0457US12490460B2Dielectric sidewall features for tuning thin film transistor (TFT) parasiticsINTEL CORP·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 0557US11610894B2Capacitor separations in dielectric layersINTEL CORP·Filed 2019·Granted Mar 21, 2023·0 cites·20 claims
- 0657US2025210509A1Single damascene via profiles for advanced integrated circuit structure fabricationINTEL CORP·Filed 2023·Application pending·0 cites
- 0757US2025220986A1Airgap spacer wrapped around a contactINTEL CORP·Filed 2023·Application pending·0 cites
- 0856US2025006495A1And double patterning strategy with printed erasable dummificationINTEL CORP·Filed 2023·Application pending·0 cites
- 0954US12484281B2Topside plugs for epitaxial contact formationINTEL CORP·Filed 2022·Granted Nov 25, 2025·0 cites·20 claims
- 1054US11832438B2Capacitor connections in dielectric layersINTEL CORP·Filed 2019·Granted Nov 28, 2023·0 cites·20 claims
- 1154US2025098179A1Memory layers at opposing sides of a complementary metal-oxide semiconductor layerSHARMA ABHISHEK A·Filed 2023·Application pending·0 cites
- 1254US2025204042A1Backside self-aligned backbone for forksheet transistorsINTEL CORP·Filed 2023·Application pending·0 cites
- 1354US2025210412A1Recessed oxide and seam-first etch for air-gapped isolation wallsINTEL CORP·Filed 2023·Application pending·0 cites
- 1454US2024312986A1Integrated circuit structures having self-aligned uniform grid metal gate and trench contact plug for tub gatesINTEL CORP·Filed 2023·Application pending·0 cites
- 1554US2024332290A1Transistor with channel-symmetric gateINTEL CORP·Filed 2023·Application pending·0 cites
- 1653US2024203869A1Integrated circuit devices with hybrid metal linesINTEL CORP·Filed 2022·Application pending·0 cites
- 1753US2024113019A1Split via structures coupled to conductive lines for advanced integrated circuit structure fabricationINTEL CORP·Filed 2022·Application pending·0 cites
- 1853US2025006810A1Transistor with channel-symmetric gateINTEL CORP·Filed 2023·Application pending·0 cites
- 1951US12414327B2Lateral confinement of source drain epitaxial growth in non-planar transistor for cell height scalingINTEL CORP·Filed 2021·Granted Sep 9, 2025·0 cites·19 claims
- 2050US2024113106A1Etch stop layer for metal gate cutINTEL CORP·Filed 2022·Application pending·0 cites
- 2150US2025081597A1Integrated circuit structures having uniform grid metal gate and trench contact plugINTEL CORP·Filed 2023·Application pending·0 cites
- 2249US2024071913A1Double-decked interconnect featuresINTEL CORP·Filed 2022·Application pending·0 cites
- 2349US2024105589A1Integrated circuit (ic) device with metal layer including staggered metal linesINTEL CORP·Filed 2022·Application pending·0 cites
- 2449US2024096785A1Integrated circuit (ic) device with hybrid metal layerINTEL CORP·Filed 2022·Application pending·0 cites
- 2548US11563107B2Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmaskINTEL CORP·Filed 2019·Granted Jan 24, 2023·0 cites·25 claims
- 2645US11652047B2Intermediate separation layers at the back-end-of-lineINTEL CORP·Filed 2019·Granted May 16, 2023·0 cites·19 claims
- 2742US2020411635A1Air gaps and capacitors in dielectric layersINTEL CORP·Filed 2019·Application pending·0 cites
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