Inventor

PARK CHANRO

US327 patents

⚠️ This page may combine multiple inventors who share the name “PARK CHANRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARK CHANRO

GLOBALFOUNDRIES INC

Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Nanosheet field-effect transistor with full dielectric isolation

Self-aligned wrap-around contacts for nanosheet devices

Method and structure of forming self-aligned RMG gate for VFET

Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Self-aligned gate-first VFETs using a gate spacer recess

Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices

Gate and source/drain contact structures positioned above an active region of a transistor device

Gate contact structure positioned above an active region of a transistor device

Vertical field effect transistor formation with critical dimension control

Middle of the line (MOL) contacts with two-dimensional self-alignment

Fin cut with alternating two color fin hardmask

Methods of forming a gate contact for a semiconductor device above the active region

Gate cut method for replacement metal gate integration

Method of forming inner spacers on a nano-sheet/wire device

Method of controlling VFET channel length

Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices

Dual thick EG oxide integration under aggressive SG fin pitch

Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers

Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark

Methods for selectively removing a fin when forming FinFET devices

Methods of forming transistor devices with different threshold voltages and the resulting products

Semiconductor device with a gate contact positioned above the active region

Methods of forming gate structure of semiconductor devices and the resulting devices

Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar

Replacement metal gate patterning for nanosheet devices

Self-aligned gate cut isolation

Dual mandrels to enable variable fin pitch

Method of forming air-gap spacers and gate contact over active region and the resulting device

Gate cut method after source/drain metallization

Gate cut in replacement metal gate process

Contacts formed with self-aligned cuts

Air-gap spacers for field-effect transistors

Fin-type field effect transistors (FINFETS) with replacement metal gates and methods

IBM

Air gap spacer formation for nano-scale semiconductor devices

Air gap spacer formation for nano-scale semiconductor devices

Mask schemes for patterning magnetic tunnel junctions

Integration of air spacer with self-aligned contact in transistor

Transistor with robust air spacer

Vertical stacked nanosheet CMOS transistors with different work function metals

Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness

Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts

Reduced source/drain coupling for CFET

Embedded anti-fuses for small scale applications

Replacement contact formation for gate contact over active region with selective metal growth

Non-self aligned gate contacts formed over the active region of a transistor

INFINEON TECHNOLOGIES AG

Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition

Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory

Recessed metal lines for protective enclosure in integrated circuits

GLOBALFOUNDRIES US INC

Gate-all-around field effect transistors with robust inner spacers and methods