Inventor · disambiguated record
Gabor Mezoesi
Also filed as: MEZOESI GABOR
12 granted patents·15 citations·filing 2016–2020
85Inventor score
Files withINFINEON TECHNOLOGIES AUSTRIA AG12
Top patents by PatentIndex Score
12 records- 0188US10811529B2Transistor device with gate resistorINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2019·Granted Oct 20, 2020·5 cites·16 claims
- 0288US9711357B1Method of manufacturing a semiconductor device with epitaxial layers and an alignment structureINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2016·Granted Jul 18, 2017·6 cites·19 claims
- 0382US10923432B2Method of manufacturing a semiconductor device with epitaxial layers and an alignment markINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2020·Granted Feb 16, 2021·1 cites·18 claims
- 0472US10411126B2Semiconductor device having a first through contact structure in ohmic contact with the gate electrodeINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2018·Granted Sep 10, 2019·1 cites·11 claims
- 0572US10374032B2Field-effect semiconductor device having N and P-doped pillar regionsINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2018·Granted Aug 6, 2019·1 cites·14 claims
- 0669US11329126B2Method of manufacturing a superjunction semiconductor deviceINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2018·Granted May 10, 2022·1 cites·20 claims
- 0767US10600740B2Method of manufacturing a semiconductor device with epitaxial layers and an alignment markINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2019·Granted Mar 24, 2020·0 cites·19 claims
- 0863US10658497B2Method for manufacturing semiconductor devices with superjunction structuresINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2018·Granted May 19, 2020·0 cites·25 claims
- 0959US10236258B2Method of manufacturing a semiconductor device with epitaxial layers and an alignment markINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2016·Granted Mar 19, 2019·0 cites·11 claims
- 1058US10957788B2Semiconductor devices with superjunction structuresINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2020·Granted Mar 23, 2021·0 cites·19 claims
- 1148US11374125B2Vertical transistor device having a discharge region comprising at least one lower dose section and located at least partially below a gate electrode padINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2020·Granted Jun 28, 2022·0 cites·15 claims
- 1243US10211300B2Method of forming a semiconductor deviceINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2017·Granted Feb 19, 2019·0 cites·21 claims
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