Inventor · disambiguated record
Alaa R. Alameldeen
Also filed as: ALAMELDEEN ALAA · ALAMELDEEN ALAA R
40 granted patents·18 pending applications·208 citations·filing 2005–2025
96Inventor score
Files withINTEL CORP49ALAMELDEEN ALAA R3WILKERSON CHRISTOPHER B2CHISHTI ZESHAN A1KHELLAH MUHAMMAD M1
Top patents by PatentIndex Score
58 records- 0197US8966345B2Selective error correction in memory to reduce power consumptionINTEL CORP·Filed 2012·Granted Feb 24, 2015·52 cites·23 claims
- 0294US9703708B2System and method for thread scheduling on reconfigurable processor coresINTEL CORP·Filed 2013·Granted Jul 11, 2017·25 cites·18 claims
- 0394US8640005B2Method and apparatus for using cache memory in a system that supports a low power stateWILKERSON CHRISTOPHER B·Filed 2010·Granted Jan 28, 2014·39 cites·22 claims
- 0492US9921972B2Method and apparatus for implementing a heterogeneous memory subsystemINTEL CORP·Filed 2016·Granted Mar 20, 2018·8 cites·19 claims
- 0591US9472248B2Method and apparatus for implementing a heterogeneous memory subsystemINTEL CORP·Filed 2014·Granted Oct 18, 2016·14 cites·22 claims
- 0690US9583182B1Multi-level memory managementINTEL CORP·Filed 2016·Granted Feb 28, 2017·9 cites·21 claims
- 0785US8276142B2Hardware support for thread scheduling on multi-core processorsALAMELDEEN ALAA R·Filed 2009·Granted Sep 25, 2012·16 cites·23 claims
- 0884US10802883B2Method, system, and device for near-memory processing with cores of a plurality of sizesINTEL CORP·Filed 2018·Granted Oct 13, 2020·4 cites·14 claims
- 0984US9417879B2Systems and methods for managing reconfigurable processor coresINTEL CORP·Filed 2013·Granted Aug 16, 2016·6 cites·19 claims
- 1083US9223710B2Read-write partitioning of cache memoryINTEL CORP·Filed 2013·Granted Dec 29, 2015·11 cites·15 claims
- 1182US2025315259A1Techniques for decoupled access-execute near-memory processingINTEL CORP·Filed 2025·Application pending·0 cites
- 1279US7412564B2Adaptive cache compression systemWISCONSIN ALUMNI RES FOUND·Filed 2005·Granted Aug 12, 2008·9 cites·30 claims
- 1378US12393421B2Techniques for decoupled access-execute near-memory processingINTEL CORP·Filed 2023·Granted Aug 19, 2025·0 cites·20 claims
- 1478US11074188B2Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memoryINTEL CORP·Filed 2019·Granted Jul 27, 2021·2 cites·20 claims
- 1572US10884927B2Cache architecture using way ID to reduce near memory traffic in a two-level memory systemINTEL CORP·Filed 2018·Granted Jan 5, 2021·1 cites·23 claims
- 1671US10877890B2Providing dead-block prediction for determining whether to cache data in cache devicesINTEL CORP·Filed 2018·Granted Dec 29, 2020·2 cites·20 claims
- 1767US8245111B2Performing multi-bit error correction on a cache lineCHISHTI ZESHAN A·Filed 2008·Granted Aug 14, 2012·6 cites·23 claims
- 1866US10048868B2Replacement of a block with a compressed block to increase capacity of a memory-side cacheINTEL CORP·Filed 2016·Granted Aug 14, 2018·1 cites·25 claims
- 1964US11853758B2Techniques for decoupled access-execute near-memory processingINTEL CORP·Filed 2019·Granted Dec 26, 2023·0 cites·16 claims
- 2060US8806285B2Dynamically allocatable memory error mitigationALAMELDEEN ALAA R·Filed 2012·Granted Aug 12, 2014·1 cites·30 claims
- 2158US2021056030A1Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2020·Application pending·0 cites
- 2255US12106104B2Processor instructions for data compression and decompressionINTEL CORP·Filed 2020·Granted Oct 1, 2024·0 cites·25 claims
- 2355US11681533B2Restricted speculative execution mode to prevent observable side effectsINTEL CORP·Filed 2019·Granted Jun 20, 2023·0 cites·15 claims
- 2452US12001346B2Device, method and system to supplement a skewed cache with a victim cacheINTEL CORP·Filed 2020·Granted Jun 4, 2024·0 cites·20 claims
- 2552US11544093B2Virtual machine replication and migrationINTEL CORP·Filed 2019·Granted Jan 3, 2023·0 cites·18 claims
- 2652US11188467B2Multi-level system memory with near memory capable of storing compressed cache linesINTEL CORP·Filed 2017·Granted Nov 30, 2021·0 cites·12 claims
- 2751US12271305B2Two-level main memory hierarchy managementINTEL CORP·Filed 2021·Granted Apr 8, 2025·0 cites·19 claims
- 2851US11526448B2Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinningINTEL CORP·Filed 2019·Granted Dec 13, 2022·0 cites·18 claims
- 2951US9251096B2Data compression in processor cachesINTEL CORP·Filed 2013·Granted Feb 2, 2016·0 cites·20 claims
- 3050US8868836B2Reducing minimum operating voltage through hybrid cache designKHELLAH MUHAMMAD M·Filed 2007·Granted Oct 21, 2014·2 cites·19 claims
- 3148US8719502B2Adaptive self-repairing cacheWILKERSON CHRISTOPHER B·Filed 2012·Granted May 6, 2014·0 cites·20 claims
- 3247US11416248B2Method and system for efficient floating-point compressionINTEL CORP·Filed 2020·Granted Aug 16, 2022·0 cites·21 claims
- 3346US10108549B2Method and apparatus for pre-fetching data in a system having a multi-level system memoryINTEL CORP·Filed 2015·Granted Oct 23, 2018·0 cites·17 claims
- 3446US9921961B2Multi-level memory managementINTEL CORP·Filed 2017·Granted Mar 20, 2018·0 cites·18 claims
- 3546US2020410094A1Hardware load hardening for speculative side-channel attacksINTEL CORP·Filed 2019·Application pending·0 cites
- 3646US2019163628A1Multi-level system memory with a battery backed up portion of a non volatile memory levelINTEL CORP·Filed 2019·Application pending·0 cites
- 3745US10691602B2Adaptive granularity for reducing cache coherence overheadINTEL CORP·Filed 2018·Granted Jun 23, 2020·0 cites·20 claims
- 3845US10417135B2Near memory miss prediction to reduce memory access latencyINTEL CORP·Filed 2017·Granted Sep 17, 2019·0 cites·22 claims
- 3945US2021200552A1Apparatus and method for non-speculative resource deallocationINTEL CORP·Filed 2019·Application pending·0 cites
- 4044US10860244B2Method and apparatus for multi-level memory early page demotionINTEL CORP·Filed 2017·Granted Dec 8, 2020·0 cites·15 claims
- 4144US10452312B2Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memoryINTEL CORP·Filed 2016·Granted Oct 22, 2019·0 cites·25 claims
- 4243US9292449B2Cache memory data compression and decompressionALAMELDEEN ALAA R·Filed 2013·Granted Mar 22, 2016·0 cites·23 claims
- 4343US2020226124A1Edge batch reordering for streaming graph analyticsINTEL CORP·Filed 2020·Application pending·0 cites
- 4441US10261901B2Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memoryINTEL CORP·Filed 2015·Granted Apr 16, 2019·0 cites·17 claims
- 4541US2022206818A1Hardening execution hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4641US2022207154A1Dynamic mitigation of speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4741US2022207138A1Hardening store hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4841US2022207146A1Hardening load hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 4941US2022207148A1Hardening branch hardware against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
- 5041US2022207147A1Hardening registers against speculation vulnerabilitiesINTEL CORP·Filed 2020·Application pending·0 cites
Showing the top 50 of 58 patent records by PatentIndex Score.
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