Inventor · disambiguated record
Ranko Scepanovic
Also filed as: SCEPANOVIC RANKO · SCEPANOVIC RANKO L
164 granted patents·3 pending applications·7,968 citations·filing 1993–2015
99Inventor score
Top patents by PatentIndex Score
167 records- 0198US5777360AHexagonal field programmable gate array architectureLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·338 cites·49 claims
- 0297US6026223AAdvanced modular cell placement system with overlap remover with minimal noiseFiled 1996·Granted Feb 15, 2000·269 cites·20 claims
- 0397US5822214ACAD for hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Oct 13, 1998·297 cites·5 claims
- 0497US5495419AIntegrated circuit physical design automation system utilizing optimization process decomposition and parallel processingLSI LOGIC CORP·Filed 1994·Granted Feb 27, 1996·199 cites·17 claims
- 0596US6407434B1Hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Jun 18, 2002·245 cites·4 claims
- 0696US5650653AMicroelectronic integrated circuit including triangular CMOS "nand" gate deviceLSI LOGIC CORP·Filed 1995·Granted Jul 22, 1997·175 cites·47 claims
- 0796US5636125AComputer implemented method for producing optimized cell placement for integrated circiut chipLSI LOGIC CORP·Filed 1995·Granted Jun 3, 1997·196 cites·17 claims
- 0894US5811863ATransistors having dynamically adjustable characteristicsLSI LOGIC CORP·Filed 1995·Granted Sep 22, 1998·202 cites·47 claims
- 0993US6553370B1Flexible search engine having sorted binary search tree for perfect matchLSI LOGIC CORP·Filed 2000·Granted Apr 22, 2003·114 cites·27 claims
- 1093US6324674B2Method and apparatus for parallel simultaneous global and detail routingLSI LOGIC CORP·Filed 1998·Granted Nov 27, 2001·206 cites·36 claims
- 1193US5973376AArchitecture having diamond shaped or parallelogram shaped cellsLSI LOGIC CORP·Filed 1995·Granted Oct 26, 1999·157 cites·9 claims
- 1293US5742086AHexagonal DRAM arrayLSI LOGIC CORP·Filed 1995·Granted Apr 21, 1998·162 cites·40 claims
- 1392US6564211B1Fast flexible search engine for longest prefix matchLSI LOGIC CORP·Filed 2000·Granted May 13, 2003·80 cites·20 claims
- 1492US6155725ACell placement representation and transposition for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Dec 5, 2000·174 cites·24 claims
- 1592US5914887ACongestion based cost factor computing apparatus for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Jun 22, 1999·176 cites·27 claims
- 1691US6499003B2Method and apparatus for application of proximity correction with unitary segmentationLSI LOGIC CORP·Filed 1998·Granted Dec 24, 2002·88 cites·13 claims
- 1791US6292929B2Advanced modular cell placement systemLSI LOGIC CORP·Filed 1999·Granted Sep 18, 2001·142 cites·22 claims
- 1891US6289495B1Method and apparatus for local optimization of the global routingLSI LOGIC CORP·Filed 1998·Granted Sep 11, 2001·166 cites·20 claims
- 1991US5889329ATri-directional interconnect architecture for SRAMLSI LOGIC CORP·Filed 1995·Granted Mar 30, 1999·135 cites·65 claims
- 2091US5578840AMicroelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometryLIS LOGIC CORP·Filed 1994·Granted Nov 26, 1996·188 cites·9 claims
- 2190US6197456B1Mask having an arbitrary complex transmission functionLSI LOGIC CORP·Filed 1999·Granted Mar 6, 2001·90 cites·29 claims
- 2290US6067409AAdvanced modular cell placement systemLSI LOGIC CORP·Filed 1997·Granted May 23, 2000·153 cites·23 claims
- 2389US6253363B1Net routing using basis element decompositionLSI LOGIC CORP·Filed 1998·Granted Jun 26, 2001·153 cites·24 claims
- 2489US6230306B1Method and apparatus for minimization of process defects while routingLSI LOGIC CORP·Filed 1998·Granted May 8, 2001·148 cites·31 claims
- 2589US6175950B1Method and apparatus for hierarchical global routing descendLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·157 cites·19 claims
- 2689US6171731B1Hybrid aerial image simulationLSI LOGIC CORP·Filed 1999·Granted Jan 9, 2001·103 cites·19 claims
- 2789US5557533ACell placement alteration apparatus for integrated circuit chip physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Sep 17, 1996·118 cites·37 claims
- 2888US5872380AHexagonal sense cell architectureLSI LOGIC CORP·Filed 1995·Granted Feb 16, 1999·106 cites·27 claims
- 2987US6247167B1Method and apparatus for parallel Steiner tree routingLSI LOGIC CORP·Filed 1998·Granted Jun 12, 2001·131 cites·82 claims
- 3087US5898597AIntegrated circuit floor plan optimization systemLSI LOGIC CORP·Filed 1997·Granted Apr 27, 1999·133 cites·20 claims
- 3186US6123736AMethod and apparatus for horizontal congestion removalLSI LOGIC CORP·Filed 1997·Granted Sep 26, 2000·119 cites·44 claims
- 3285US6493658B1Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithmsLSI LOGIC CORP·Filed 1994·Granted Dec 10, 2002·104 cites·33 claims
- 3385US6068662AMethod and apparatus for congestion removalLSI LOGIG CORP·Filed 1997·Granted May 30, 2000·129 cites·29 claims
- 3485US6058254AMethod and apparatus for vertical congestion removalLSI LOGIC CORP·Filed 1997·Granted May 2, 2000·118 cites·37 claims
- 3583US6587990B1Method and apparatus for formula area and delay minimizationLSI LOGIC CORP·Filed 2000·Granted Jul 1, 2003·36 cites·12 claims
- 3683US5903461AMethod of cell placement for an integrated circuit chip comprising chaotic placement and moving windowsLSI LOGIC CORP·Filed 1997·Granted May 11, 1999·68 cites·40 claims
- 3783US5745363AOptimization processing for integrated circuit physical design automation system using optimally switched cost function computationsLSI LOGIC CORP·Filed 1996·Granted Apr 28, 1998·70 cites·23 claims
- 3882US8516425B2Method and computer program for generating grounded shielding wires for signal wiringNIKITIN ANDREY·Filed 2012·Granted Aug 20, 2013·7 cites·25 claims
- 3982US6735600B1Editing protocol for flexible search enginesLSI LOGIC CORP·Filed 2001·Granted May 11, 2004·35 cites·18 claims
- 4082US5491641ATowards optical steiner tree routing in the presence of rectilinear obstaclesLSI LOGIC CORP·Filed 1993·Granted Feb 13, 1996·77 cites·4 claims
- 4181US9024657B2Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smallerEASIC CORP·Filed 2012·Granted May 5, 2015·9 cites·18 claims
- 4281US7415686B2Memory timing model with back-annotatingLSI CORP·Filed 2005·Granted Aug 19, 2008·12 cites·25 claims
- 4381US6223332B1Advanced modular cell placement system with overlap remover with minimal noiseLSI LOGIC CORP·Filed 2000·Granted Apr 24, 2001·28 cites·21 claims
- 4481US5742510ASimultaneous placement and routing (SPAR) method for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Apr 21, 1998·61 cites·28 claims
- 4580US7340706B2Method and system for analyzing the quality of an OPC maskLSI LOGIC CORP·Filed 2005·Granted Mar 4, 2008·7 cites·24 claims
- 4680US6154874AMemory-saving method and apparatus for partitioning high fanout netsLSI LOGIC CORP·Filed 1998·Granted Nov 28, 2000·91 cites·28 claims
- 4780US6134702APhysical design automation system and process for designing integrated circuit chips using multiway partitioning with constraintsLSI LOGIC CORP·Filed 1997·Granted Oct 17, 2000·90 cites·22 claims
- 4880US5875117ASimultaneous placement and routing (SPAR) method for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Feb 23, 1999·91 cites·32 claims
- 4979US7389484B2Method and apparatus for tiling memories in integrated circuit layoutLSI CORP·Filed 2005·Granted Jun 17, 2008·10 cites·20 claims
- 5079US6532585B1Method and apparatus for application of proximity correction with relative segmentationLSI LOGIC CORP·Filed 2000·Granted Mar 11, 2003·15 cites·35 claims
Showing the top 50 of 167 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →