Inventor · disambiguated record
Garrett Stephen Koch
Also filed as: KOCH GARRETT S · KOCH GARRETT STEPHEN
20 granted patents·760 citations·filing 1991–2008
96Inventor score
Files withIBM20
Top patents by PatentIndex Score
20 records- 0195US6430073B1Dram CAM cell with hidden refreshIBM·Filed 2000·Granted Aug 6, 2002·95 cites·19 claims
- 0295US5859804AMethod and apparatus for real time two dimensional redundancy allocationIBM·Filed 1997·Granted Jan 12, 1999·119 cites·4 claims
- 0395US5535164ABIST tester for multiple memoriesIBM·Filed 1995·Granted Jul 9, 1996·149 cites·18 claims
- 0492US5796745AMemory array built-in self test circuit for testing multi-port memory arraysIBM·Filed 1996·Granted Aug 18, 1998·105 cites·20 claims
- 0586US6026505AMethod and apparatus for real time two dimensional redundancy allocationIBM·Filed 1991·Granted Feb 15, 2000·55 cites·11 claims
- 0682US5784323ATest converage of embedded memories on semiconductor substratesIBM·Filed 1997·Granted Jul 21, 1998·50 cites·17 claims
- 0775US5317573AApparatus and method for real time data error capture and compression redundancy analysisIBM·Filed 1992·Granted May 31, 1994·44 cites·1 claims
- 0872US7003704B2Two-dimensional redundancy calculationIBM·Filed 2002·Granted Feb 21, 2006·20 cites·13 claims
- 0969US8006153B2Multiple uses for BIST test latchesIBM·Filed 2008·Granted Aug 23, 2011·5 cites·9 claims
- 1069US6282144B1Multi-ported memory with asynchronous and synchronous protocolIBM·Filed 2000·Granted Aug 28, 2001·14 cites·25 claims
- 1169US5790564AMemory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method thereforIBM·Filed 1995·Granted Aug 4, 1998·25 cites·3 claims
- 1269US5563833AUsing one memory to supply addresses to an associated memory during testingIBM·Filed 1995·Granted Oct 8, 1996·23 cites·17 claims
- 1364US7574642B2Multiple uses for BIST test latchesIBM·Filed 2005·Granted Aug 11, 2009·4 cites·6 claims
- 1452US5771242AMemory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method thereforIBM·Filed 1996·Granted Jun 23, 1998·12 cites·12 claims
- 1549US5761213AMethod and apparatus to determine erroneous value in memory cells using data compressionIBM·Filed 1996·Granted Jun 2, 1998·11 cites·17 claims
- 1648US7117400B2Memory device with data line steering and bitline redundancyIBM·Filed 2002·Granted Oct 3, 2006·5 cites·26 claims
- 1747US5918003AEnhanced built-in self-test circuit and methodIBM·Filed 1997·Granted Jun 29, 1999·12 cites·3 claims
- 1846US5745498ARapid compare of two binary numbersIBM·Filed 1996·Granted Apr 28, 1998·8 cites·25 claims
- 1933US7562267B2Methods and apparatus for testing a memoryIBM·Filed 2004·Granted Jul 14, 2009·0 cites·50 claims
- 2033US5093584ASelf calibrating timing circuitIBM·Filed 1991·Granted Mar 3, 1992·4 cites·10 claims
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