Inventor · disambiguated record
Loi N. Nguyen
Also filed as: NGUYEN LOI · NGUYEN LOI N · NGUYEN LOI NGOC
44 granted patents·1 pending application·440 citations·filing 1992–2023
98Inventor score
Files withST MICROELECTRONICS INC25SGS THOMSON MICROELECTRONICS11MOHANAKRISHNASWAMY VENKATESH4AKSELOS S A1CHANDLER RAND C1
Top patents by PatentIndex Score
45 records- 0195US11837509B1Method of manufacturing and packaging silicon photonics integrated circuit dies in wafer formINPHI CORP·Filed 2020·Granted Dec 5, 2023·8 cites·9 claims
- 0276US7943410B2Embedded microelectromechanical systems (MEMS) semiconductor substrate and related method of formingST MICROELECTRONICS INC·Filed 2008·Granted May 17, 2011·6 cites·19 claims
- 0372US6096634AMethod of patterning a submicron semiconductor layerST MICROELECTRONICS INC·Filed 1997·Granted Aug 1, 2000·35 cites·11 claims
- 0472US5972188AMembrane loader for gel electrophoresisGENETIC BIOSYSTEMS INC·Filed 1996·Granted Oct 26, 1999·46 cites·8 claims
- 0571US5439846ASelf-aligned method for forming contact with zero offset to gateSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Aug 8, 1995·40 cites·27 claims
- 0667US5914518AMethod of forming a metal contact to landing pad structure in an integrated circuitST MICROELECTRONICS INC·Filed 1996·Granted Jun 22, 1999·22 cites·15 claims
- 0767US5705427AMethod of forming a landing pad structure in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Jan 6, 1998·30 cites·33 claims
- 0867US5323047AStructure formed by a method of patterning a submicron semiconductor layerSGS THOMSON MICROELECTRONICS·Filed 1992·Granted Jun 21, 1994·34 cites·9 claims
- 0966US5702979AMethod of forming a landing pad structure in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1994·Granted Dec 30, 1997·19 cites·35 claims
- 1065US5894160AMethod of forming a landing pad structure in an integrated circuitST MICROELECTRONICS INC·Filed 1996·Granted Apr 13, 1999·18 cites·18 claims
- 1162US8193595B2Method of forming a die having an IC region adjacent a MEMS regionMOHANAKRISHNASWAMY VENKATESH·Filed 2009·Granted Jun 5, 2012·2 cites·22 claims
- 1260US6514811B2Method for memory masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 2001·Granted Feb 4, 2003·6 cites·13 claims
- 1358US8680631B2High aspect ratio capacitively coupled MEMS devicesST MICROELECTRONICS INC·Filed 2013·Granted Mar 25, 2014·0 cites·16 claims
- 1457US8022491B2High aspect ratio all SiGe capacitively coupled MEMS devicesST MICROELECTRONICS INC·Filed 2009·Granted Sep 20, 2011·0 cites·26 claims
- 1556USRE36938EMethod of forming a landing pad structure in an integrated circuitST MICROELECTRONICS INC·Filed 1998·Granted Oct 31, 2000·12 cites·35 claims
- 1656US5885871AMethod of making EEPROM cell structureSTMICROLELECTRONICS INC·Filed 1997·Granted Mar 23, 1999·17 cites·21 claims
- 1755US5956615AMethod of forming a metal contact to landing pad structure in an integrated circuitST MICROELECTRONICS INC·Filed 1994·Granted Sep 21, 1999·13 cites·29 claims
- 1853US8432006B2High aspect ratio capacitively coupled MEMS devicesMOHANAKRISHNASWAMY VENKATESH·Filed 2011·Granted Apr 30, 2013·0 cites·18 claims
- 1952US6661064B2Memory masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 2002·Granted Dec 9, 2003·3 cites·5 claims
- 2050US6812142B1Method and interlevel dielectric structure for improved metal step coverageST MICROELECTRONICS INC·Filed 2000·Granted Nov 2, 2004·4 cites·16 claims
- 2149USRE45286EEmbedded microelectromechanical systems (MEMS) semiconductor substrate and related method of formingST MICROELECTRONICS INC·Filed 2013·Granted Dec 9, 2014·0 cites·37 claims
- 2249US8853850B2MEMS packaging scheme using dielectric fenceST MICROELECTRONICS INC·Filed 2013·Granted Oct 7, 2014·0 cites·15 claims
- 2349US8405202B2MEMS packaging scheme using dielectric fenceMOHANAKRISHNASWAMY VENKATESH·Filed 2009·Granted Mar 26, 2013·0 cites·18 claims
- 2448US6051864AMemory masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 1997·Granted Apr 18, 2000·10 cites·15 claims
- 2548US5597983AProcess of removing polymers in semiconductor viasSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Jan 28, 1997·14 cites·5 claims
- 2647US6093963ADual landing pad structure including dielectric pocketST MICROELECTRONICS INC·Filed 1997·Granted Jul 25, 2000·12 cites·20 claims
- 2745US8853802B2Method of forming a die having an IC region adjacent a MEMS regionMOHANAKRISHNASWAMY VENKATESH·Filed 2012·Granted Oct 7, 2014·0 cites·20 claims
- 2844US5793114ASelf-aligned method for forming contact with zero offset to gateSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Aug 11, 1998·10 cites·32 claims
- 2944US5423939AMethod for forming contact plugs in integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Jun 13, 1995·11 cites·16 claims
- 3042US5870330AMethod of making and structure of SRAM storage cell with N channel thin film transistor load devicesST MICROELECTRONICS INC·Filed 1996·Granted Feb 9, 1999·5 cites·14 claims
- 3141US12425112B2Signal power validatorCHANDLER RAND C·Filed 2023·Granted Sep 23, 2025·0 cites·7 claims
- 3241US6518620B2EEPROM memory cell with increased dielectric integrityST MICROELECTRONICS INC·Filed 1998·Granted Feb 11, 2003·6 cites·10 claims
- 3341US6472261B2Method of forming an integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosureST MICROELECTRONICS INC·Filed 1999·Granted Oct 29, 2002·8 cites·16 claims
- 3440US6057604AIntegrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosureST MICROELECTRONICS INC·Filed 1997·Granted May 2, 2000·7 cites·20 claims
- 3539USRE41670ESram cell fabrication with interlevel Dielectric planarizationST MICROELECTRONICS INC·Filed 2000·Granted Sep 14, 2010·0 cites·34 claims
- 3639US6284584B1Method of masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 1997·Granted Sep 4, 2001·5 cites·6 claims
- 3739US6107194AMethod of fabricating an integrated circuitST MICROELECTRONICS INC·Filed 1997·Granted Aug 22, 2000·5 cites·24 claims
- 3839US5395785ASRAM cell fabrication with interlevel dielectric planarizationSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Mar 7, 1995·7 cites·18 claims
- 3937US5945738ADual landing pad structure in an integrated circuitST MICROELECTRONICS INC·Filed 1996·Granted Aug 31, 1999·7 cites·5 claims
- 4037US5412868AProcess of removing polymers in semiconductor viasSGS THOMSON MICROELECTRONICS·Filed 1994·Granted May 9, 1995·8 cites·8 claims
- 4137US2018373820A1Methods and Systems for Constructing and Analyzing Component-Based Models of Engineering Systems Having Linear and Nonlinear RegionsAKSELOS S A·Filed 2017·Application pending·0 cites
- 4236US5710461ASRAM cell fabrication with interlevel dielectric planarizationSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Jan 20, 1998·4 cites·18 claims
- 4334US5909636AMethod of forming a landing pad structure in an integrated circuitST MICROELECTRONICS INC·Filed 1997·Granted Jun 1, 1999·3 cites·33 claims
- 4432US6251713B1Method of making an SRAM storage cell with N channel thin film transistor load devicesST MICROELECTRONICS INC·Filed 1997·Granted Jun 26, 2001·1 cites·15 claims
- 4532US5751064AIntermediate structure for integrated circuit devicesSGS THOMSON MICROELECTRONICS·Filed 1995·Granted May 12, 1998·2 cites·16 claims
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