Inventor · disambiguated record
James L. Federici
Also filed as: FEDERICI JAMES L · FEDERICI JAMES LOUIS
6 granted patents·104 citations·filing 1995–2000
83Inventor score
Technology areasG06F
Files withUNISYS CORP6
Top patents by PatentIndex Score
6 records- 0161US5875201ASecond level cache having instruction cache parity error controlUNISYS CORP·Filed 1996·Granted Feb 23, 1999·42 cites·20 claims
- 0259US6697925B1Use of a cache ownership mechanism to synchronize multiple dayclocksUNISYS CORP·Filed 2000·Granted Feb 24, 2004·7 cites·20 claims
- 0354US5915128ASerial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another registerUNISYS CORP·Filed 1997·Granted Jun 22, 1999·31 cites·17 claims
- 0448US6857049B1Method for managing flushes with the cacheUNISYS CORP·Filed 2000·Granted Feb 15, 2005·1 cites·6 claims
- 0544US5617375ADayclock carry and compare treeUNISYS CORP·Filed 1995·Granted Apr 1, 1997·18 cites·22 claims
- 0631US6055607AInterface queue with bypassing capability for main storage unitUNISYS CORP·Filed 1996·Granted Apr 25, 2000·5 cites·12 claims
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