Inventor · disambiguated record
Birendra Agarwala
Also filed as: AGARWALA BIRENDRA · AGARWALA BIRENDRA N · AGARWALA BIRENDRA NATH
21 granted patents·4 pending applications·1,895 citations·filing 1989–2010
97Inventor score
Top patents by PatentIndex Score
25 records- 0199US7397260B2Structure and method for monitoring stress-induced degradation of conductive interconnectsIBM·Filed 2005·Granted Jul 8, 2008·169 cites·12 claims
- 0297US6734090B2Method of making an edge seal for a semiconductor deviceIBM·Filed 2002·Granted May 11, 2004·605 cites·9 claims
- 0394US5376584AProcess of making pad structure for solder ball limiting metallurgy having reduced edge stressIBM·Filed 1992·Granted Dec 27, 1994·163 cites·8 claims
- 0494US5130779ASolder mass having conductive encapsulating arrangementIBM·Filed 1990·Granted Jul 14, 1992·185 cites·47 claims
- 0593US7279411B2Process for forming a redundant structureIBM·Filed 2005·Granted Oct 9, 2007·23 cites·12 claims
- 0693US6033939AMethod for providing electrically fusible links in copper interconnectionIBM·Filed 1998·Granted Mar 7, 2000·152 cites·13 claims
- 0792US5251806AMethod of forming dual height solder interconnectionsIBM·Filed 1992·Granted Oct 12, 1993·144 cites·48 claims
- 0891US6111321ABall limiting metalization process for interconnectionIBM·Filed 1995·Granted Aug 29, 2000·107 cites·3 claims
- 0988US5268072AEtching processes for avoiding edge stress in semiconductor chip solder bumpsIBM·Filed 1992·Granted Dec 7, 1993·119 cites·14 claims
- 1082US7224063B2Dual-damascene metallization interconnectionIBM·Filed 2001·Granted May 29, 2007·30 cites·6 claims
- 1182US6972209B2Stacked via-stud with improved reliability in copper metallurgyIBM·Filed 2002·Granted Dec 6, 2005·32 cites·8 claims
- 1280US7163883B2Edge seal for a semiconductor deviceIBM·Filed 2003·Granted Jan 16, 2007·27 cites·6 claims
- 1380US7138714B2Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal linesIBM·Filed 2005·Granted Nov 21, 2006·10 cites·10 claims
- 1478US7470613B2Dual damascene multi-level metallizationIBM·Filed 2007·Granted Dec 30, 2008·7 cites·19 claims
- 1576US4985310AMultilayered metallurgical structure for an electronic componentIBM·Filed 1989·Granted Jan 15, 1991·51 cites·16 claims
- 1672US8466056B2Method of forming metal interconnect structures in ultra low-k dielectricsAGARWALA BIRENDRA·Filed 2010·Granted Jun 18, 2013·4 cites·20 claims
- 1770US7639032B2Structure for monitoring stress-induced degradation of conductive interconnectsIBM·Filed 2007·Granted Dec 29, 2009·2 cites·7 claims
- 1869US6825561B1Structure and method for eliminating time dependent dielectric breakdown failure of low-k materialIBM·Filed 2003·Granted Nov 30, 2004·15 cites·16 claims
- 1969US4970570AUse of tapered head pin design to improve the stress distribution in the braze jointIBM·Filed 1989·Granted Nov 13, 1990·34 cites·20 claims
- 2057US7692439B2Structure for modeling stress-induced degradation of conductive interconnectsIBM·Filed 2008·Granted Apr 6, 2010·0 cites·6 claims
- 2151US2010176513A1Structure and method of forming metal interconnect structures in ultra low-k dielectricsIBM·Filed 2009·Application pending·0 cites
- 2250US6271599B1Wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrateIBM·Filed 1999·Granted Aug 7, 2001·16 cites·11 claims
- 2349US2007205515A1Device having a redundant structureIBM·Filed 2007·Application pending·0 cites
- 2446US2006014376A1Stacked via-stud with improved reliability in copper metallurgyIBM·Filed 2005·Application pending·0 cites
- 2536US2003134495A1Integration scheme for advanced BEOL metallization including low-k cap layer and method thereofIBM·Filed 2002·Application pending·0 cites
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