Inventor · disambiguated record
Shubhendu Sekhar Mukherjee
Also filed as: MUKHERJEE SHUBHENDU · MUKHERJEE SHUBHENDU S · MUKHERJEE SHUBHENDU SEKHAR
109 granted patents·19 pending applications·954 citations·filing 1997–2024
99Inventor score
Top patents by PatentIndex Score
128 records- 0198US11500779B1Vector prefetching for computing systemsMARVELL ASIA PTE LTD·Filed 2020·Granted Nov 15, 2022·10 cites·20 claims
- 0298US11263043B1Managing processor core synchronization using interruptsMARVELL ASIA PTE LTD·Filed 2020·Granted Mar 1, 2022·12 cites·30 claims
- 0397US11513958B1Shared mid-level data cacheMARVELL ASIA PTE LTD·Filed 2020·Granted Nov 29, 2022·7 cites·20 claims
- 0497US11126556B1History table management for a correlated prefetcherMARVELL ASIA PTE LTD·Filed 2020·Granted Sep 21, 2021·7 cites·20 claims
- 0596US11379372B1Managing prefetch lookahead distance based on memory access latencyMARVELL ASIA PTE LTD·Filed 2020·Granted Jul 5, 2022·5 cites·21 claims
- 0696US9772943B1Managing synonyms in virtual-address cachesCAVIUM INC·Filed 2016·Granted Sep 26, 2017·22 cites·36 claims
- 0795US11604873B1Noisy instructions for side-channel attack mitigationMARVELL ASIA PTE LTD·Filed 2020·Granted Mar 14, 2023·4 cites·25 claims
- 0895US11307857B2Dynamic designation of instructions as sensitive for constraining multithreaded executionMARVELL ASIA PTE LTD·Filed 2020·Granted Apr 19, 2022·3 cites·21 claims
- 0995US11176055B1Managing potential faults for speculative page table accessMARVELL INT LTD·Filed 2019·Granted Nov 16, 2021·14 cites·22 claims
- 1094US11327890B1Partitioning in a processor cacheMARVELL ASIA PTE LTD·Filed 2019·Granted May 10, 2022·11 cites·14 claims
- 1194US11263015B1Microarchitectural sensitive tag flowMARVELL ASIA PTE LTD·Filed 2020·Granted Mar 1, 2022·3 cites·50 claims
- 1293US10282299B2Managing cache partitions based on cache usage informationCAVIUM LLC·Filed 2017·Granted May 7, 2019·11 cites·20 claims
- 1393US9779028B1Managing translation invalidationCAVIUM INC·Filed 2016·Granted Oct 3, 2017·16 cites·20 claims
- 1492US10558573B1Methods and systems for distributing memory requestsCAVIUM LLC·Filed 2018·Granted Feb 11, 2020·6 cites·22 claims
- 1591US9639476B2Merged TLB structure for multiple sequential address translationsCAVIUM INC·Filed 2013·Granted May 2, 2017·15 cites·45 claims
- 1691US7243262B2Incremental checkpointing in a multi-threaded architectureINTEL CORP·Filed 2003·Granted Jul 10, 2007·67 cites·29 claims
- 1790US10013357B2Managing memory access requests with prefetch for streamsCAVIUM INC·Filed 2016·Granted Jul 3, 2018·6 cites·32 claims
- 1890US9268694B2Maintenance of cache and tags in a translation lookaside bufferCAVIUM INC·Filed 2013·Granted Feb 23, 2016·14 cites·21 claims
- 1989US11372647B2Pipelines for secure multithread executionMARVELL ASIA PTE LTD·Filed 2020·Granted Jun 28, 2022·2 cites·25 claims
- 2089US10540181B2Managing branch prediction information for different contextsMARVELL WORLD TRADE LTD·Filed 2018·Granted Jan 21, 2020·5 cites·26 claims
- 2188US11615027B2Methods and systems for distributing memory requestsMARVELL ASIA PTE LTD·Filed 2021·Granted Mar 28, 2023·1 cites·20 claims
- 2288US11036643B1Mid-level instruction cacheMARVELL ASIA PTE LTD·Filed 2019·Granted Jun 15, 2021·5 cites·12 claims
- 2388US7308607B2Periodic checkpointing in a redundantly multi-threaded architectureINTEL CORP·Filed 2003·Granted Dec 11, 2007·55 cites·40 claims
- 2488US6854075B2Simultaneous and redundantly threaded processor store instruction comparatorHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 8, 2005·55 cites·18 claims
- 2588US6792525B2Input replicator for interrupts in a simultaneous and redundantly threaded processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Sep 14, 2004·55 cites·29 claims
- 2688US6598122B2Active load address bufferHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 22, 2003·51 cites·20 claims
- 2787US11550590B2System and method for implementing strong load ordering in a processor using a circular ordering ringMARVELL ASIA PTE LTD·Filed 2022·Granted Jan 10, 2023·1 cites·42 claims
- 2887US9645941B2Collapsed address translation with multiple page sizesCAVIUM INC·Filed 2013·Granted May 9, 2017·10 cites·28 claims
- 2987US7849387B2Detecting architectural vulnerability of processor resourcesINTEL CORP·Filed 2008·Granted Dec 7, 2010·17 cites·22 claims
- 3087US7472299B2Low power arbiters in interconnection routersINTEL CORP·Filed 2005·Granted Dec 30, 2008·16 cites·26 claims
- 3186US11886882B2Pipelines for secure multithread executionMARVELL ASIA PTE LTD·Filed 2022·Granted Jan 30, 2024·1 cites·25 claims
- 3286US11269644B1System and method for implementing strong load ordering in a processor using a circular ordering ringMARVELL ASIA PTE LTD·Filed 2019·Granted Mar 8, 2022·3 cites·40 claims
- 3386US11093405B1Shared mid-level data cacheMARVELL ASIA PTE LTD·Filed 2019·Granted Aug 17, 2021·3 cites·14 claims
- 3486US7373548B2Hardware recovery in a multi-threaded architectureINTEL CORP·Filed 2003·Granted May 13, 2008·42 cites·27 claims
- 3586US6757811B1Slack fetch to improve performance in a simultaneous and redundantly threaded processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jun 29, 2004·46 cites·25 claims
- 3684US10331500B2Managing fairness for lock and unlock operations using operation prioritizationCAVIUM LLC·Filed 2017·Granted Jun 25, 2019·4 cites·32 claims
- 3784US9405702B2Caching TLB translations using a unified page table walker cacheCAVIUM INC·Filed 2014·Granted Aug 2, 2016·9 cites·24 claims
- 3883US9471509B2Managing address-independent page attributesCAVIUM INC·Filed 2015·Granted Oct 18, 2016·4 cites·28 claims
- 3983US7649845B2Handling hot spots in interconnection networksINTEL CORP·Filed 2005·Granted Jan 19, 2010·11 cites·27 claims
- 4083US7475321B2Detecting errors in directory entriesINTEL CORP·Filed 2004·Granted Jan 6, 2009·32 cites·13 claims
- 4183US6823473B2Simultaneous and redundantly threaded processor uncached load address comparator and data value replication circuitHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 23, 2004·35 cites·24 claims
- 4282US6854051B2Cycle count replication in a simultaneous and redundantly threaded processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 8, 2005·32 cites·21 claims
- 4381US11188466B2Methods and systems for distributing memory requestsMARVELL ASIA PTE LTD·Filed 2020·Granted Nov 30, 2021·1 cites·24 claims
- 4481US10248420B2Managing lock and unlock operations using active spinningCAVIUM LLC·Filed 2017·Granted Apr 2, 2019·2 cites·20 claims
- 4581US10223279B2Managing virtual-address caches for multiple memory page sizesCAVIUM LLC·Filed 2016·Granted Mar 5, 2019·3 cites·24 claims
- 4681US9870328B2Managing buffered communication between coresCAVIUM INC·Filed 2014·Granted Jan 16, 2018·6 cites·12 claims
- 4780US10817300B2Managing commit order for an external instruction relative to two unissued queued instructionsMARVELL INT LTD·Filed 2018·Granted Oct 27, 2020·2 cites·10 claims
- 4880US9501425B2Translation lookaside buffer managementCAVIUM INC·Filed 2014·Granted Nov 22, 2016·6 cites·26 claims
- 4980US7606980B2Demand-based error correctionINTEL CORP·Filed 2006·Granted Oct 20, 2009·10 cites·22 claims
- 5079US11194584B1Managing out-of-order retirement of instructionsMARVELL ASIA PTE LTD·Filed 2020·Granted Dec 7, 2021·1 cites·24 claims
Showing the top 50 of 128 patent records by PatentIndex Score.
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