Inventor

BILES STUART DAVID

GB48 patents

⚠️ This page may combine multiple inventors who share the name “BILES STUART DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BILES STUART DAVID

ADVANCED RISC MACH LTD

Handling access requests in a data processing apparatus

Managing cache coherency in a data processing apparatus

Cache management within a data processing apparatus

Instruction issue control within a multi-threaded in-order superscalar processor

Program subgraph identification

Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion

Secure mechanism to switch between different domains of operation in a data processor

Memory domain based security control with data processing systems

Memory access security management

Two-level branch prediction apparatus

Accessing items of architectural state from a register cache in a data processing apparatus when performing branch prediction operations for an indirect branch instruction

Data processing apparatus and method for performing a cache lookup in an energy efficient manner

Interrupt controller utilising programmable priority values

Data processing apparatus and method for handling corrupted data values

Controlling cleaning of data values within a hardware accelerator

Data processing apparatus and method for updating prediction data based on an operation&#39;s priority level

Multiple thread instruction fetch from different cache levels

Data processor with hardware accelerator, accelerator interface and shared memory management unit

Allocation of branch target cache resources in dependence upon program instructions within an instruction queue

Cryptographic support instructions

Cryptographic support instructions

Apparatus and method for managing capability metadata

Control of master/slave communication within an integrated circuit

Program subgraph identification

Efficiency of cache memory operations

Execution of instructions within a data processing apparatus having a plurality of processing units

Fault handling in address translation transactions

Branch prediction within a multithreaded processor

Cryptographic support instructions

Apparatus and method for performing operations on capability metadata

Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus

Support apparatus and method for processing data and using hardware support for atomic memory transactions

Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains

OEZER EMRE

Data processing apparatus and method for managing multiple program threads executed by processing circuitry

Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit

BILES STUART DAVID

Contention management for a hardware transactional memory

Store-exclusive instruction conflict resolution

PAVER NIGEL CHARLES

Cache device for coupling to a memory device and a method of operation of such a cache device

Providing secure services to a non-secure application

ÖZER EMRE

Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus

Issue policy control within a multi-threaded in-order superscalar processor

PIRY FREDERIC CLAUDE MARIE

Handling of write access requests to shared memory in a data processing apparatus

GHOSH MRINMOY

Cache miss detection in a data processing apparatus

MANSELL DAVID HENNAH

Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty

BLAAUW DAVID THEODORE

Operating parameter control of an apparatus for processing data

WILLIAMS MICHAEL JOHN

Hardware resource management within a data processing system

CRASKE SIMON JOHN

Error correction in a set associative storage device

LAYCOCK CHRISTOPHER WILLIAM

Coherency control with writeback ordering

Data processing apparatus and method for updating prediction data based on an operation's priority level