Inventor · disambiguated record
Nathaniel D. Hieter
Also filed as: HIETER NATHANIEL · HIETER NATHANIEL D · HIETER NATHANIEL DOUGLAS
19 granted patents·1 pending application·69 citations·filing 1996–2020
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0190US10970455B1Apportionment aware hierarchical timing optimizationIBM·Filed 2020·Granted Apr 6, 2021·3 cites·18 claims
- 0290US9418188B1Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Aug 16, 2016·5 cites·1 claims
- 0388US10216875B2Leverage cycle stealing within optimization flowsIBM·Filed 2017·Granted Feb 26, 2019·4 cites·8 claims
- 0487US9436791B1Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2015·Granted Sep 6, 2016·4 cites·20 claims
- 0582US9747400B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Aug 29, 2017·2 cites·1 claims
- 0682US9703914B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Jul 11, 2017·2 cites·20 claims
- 0778US10540465B2Leverage cycle stealing within optimization flowsIBM·Filed 2019·Granted Jan 21, 2020·1 cites·1 claims
- 0878US7500207B2Influence-based circuit designIBM·Filed 2006·Granted Mar 3, 2009·9 cites·20 claims
- 0976US10552562B2Leverage cycle stealing within optimization flowsIBM·Filed 2017·Granted Feb 4, 2020·1 cites·12 claims
- 1074US8234612B2Cone-aware spare cell placement using hypergraph connectivity analysisGOODMAN BENJIMAN L·Filed 2010·Granted Jul 31, 2012·4 cites·21 claims
- 1173US7178120B2Method for performing timing closure on VLSI chips in a distributed environmentIBM·Filed 2003·Granted Feb 13, 2007·19 cites·17 claims
- 1269US8302049B2Method for enabling multiple incompatible or costly timing environment for efficient timing closureMUSANTE FRANK J·Filed 2010·Granted Oct 30, 2012·4 cites·20 claims
- 1367US9785735B1Parallel incremental global routingIBM·Filed 2016·Granted Oct 10, 2017·1 cites·20 claims
- 1466US10970447B2Leverage cycle stealing within optimization flowsIBM·Filed 2019·Granted Apr 6, 2021·0 cites·13 claims
- 1561US2018239845A1Leverage cycle stealing within optimization flowsIBM·Filed 2017·Application pending·0 cites
- 1659US10210297B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Feb 19, 2019·0 cites·1 claims
- 1750US11030367B2Out-of-context feedback hierarchical large block synthesis (HLBS) optimizationIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 1849US11288425B1Path-based timing driven placement using iterative pseudo netlist changesIBM·Filed 2020·Granted Mar 29, 2022·0 cites·25 claims
- 1947US9639654B2Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuitIBM·Filed 2014·Granted May 2, 2017·0 cites·15 claims
- 2034US5877965AParallel hierarchical timing correctionIBM·Filed 1996·Granted Mar 2, 1999·10 cites·8 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →