Inventor · disambiguated record
Navid Azizi
Also filed as: AZIZI NAVID
19 granted patents·3 pending applications·187 citations·filing 2003–2022
94Inventor score
Top patents by PatentIndex Score
22 records- 0197US8565033B1Methods for calibrating memory interface circuitryMANOHARARAJAH VALAVAN·Filed 2011·Granted Oct 22, 2013·79 cites·20 claims
- 0291US8897083B1Memory interface circuitry with data strobe signal sharing capabilitiesALTERA CORP·Filed 2012·Granted Nov 25, 2014·15 cites·19 claims
- 0388US8296704B1Method and apparatus for simultaneous switching noise optimizationKIPPER MICHAEL HOWARD·Filed 2010·Granted Oct 23, 2012·14 cites·20 claims
- 0487US9679633B2Circuits and methods for DQS autogatingALTERA CORP·Filed 2016·Granted Jun 13, 2017·8 cites·20 claims
- 0585US8977998B1Timing analysis with end-of-life pessimism removalALTERA CORP·Filed 2013·Granted Mar 10, 2015·12 cites·21 claims
- 0683US9257164B2Circuits and methods for DQS autogatingALTERA CORP·Filed 2013·Granted Feb 9, 2016·7 cites·23 claims
- 0777US9058436B1Method and system for reducing the effect of component agingALTERA CORP·Filed 2012·Granted Jun 16, 2015·4 cites·19 claims
- 0876US8443321B1Pessimism removal in the modeling of simultaneous switching noiseFENDER JOSHUA DAVID·Filed 2008·Granted May 14, 2013·8 cites·23 claims
- 0975US10224908B1Low frequency variation calibration circuitryFENDER JOSHUA DAVID·Filed 2011·Granted Mar 5, 2019·4 cites·8 claims
- 1072US7307905B2Low leakage asymmetric SRAM cell devicesUNIV TORONTO·Filed 2003·Granted Dec 11, 2007·22 cites·8 claims
- 1168US9047215B1Method and system for reducing the effect of component recoveryALTERA CORP·Filed 2012·Granted Jun 2, 2015·2 cites·21 claims
- 1268US8627254B2Method and apparatus for simultaneous switching noise optimizationKIPPER MICHAEL HOWARD·Filed 2012·Granted Jan 7, 2014·2 cites·20 claims
- 1366US8694946B1Simultaneous switching noise optimizationFENDER JOSHUA DAVID·Filed 2009·Granted Apr 8, 2014·3 cites·18 claims
- 1466US8151233B1Circuit design with incremental simultaneous switching noise analysisAZIZI NAVID·Filed 2009·Granted Apr 3, 2012·4 cites·20 claims
- 1563US9698795B1Supporting pseudo open drain input/output standards in a programmable logic deviceALTERA CORP·Filed 2013·Granted Jul 4, 2017·1 cites·19 claims
- 1660US8302058B1Reducing simultaneous switching noise in an integrated circuit design during placementKIPPER MICHAEL HOWARD·Filed 2009·Granted Oct 30, 2012·2 cites·18 claims
- 1753US9948307B2Supporting pseudo open drain input/output standards in a programmable logic deviceALTERA CORP·Filed 2017·Granted Apr 17, 2018·0 cites·20 claims
- 1853US2017270995A1Circuits and methods for dqs autogatingALTERA CORP·Filed 2017·Application pending·0 cites
- 1947US2022221986A1Fabric memory network-on-chipWEBER SCOTT JEREMY·Filed 2022·Application pending·0 cites
- 2044US9684742B1Method and apparatus for performing timing analysis on calibrated pathsAZIZI NAVID·Filed 2010·Granted Jun 20, 2017·0 cites·35 claims
- 2136US10320393B2Dynamic multicycles for core-periphery timing closureINTEL CORP·Filed 2017·Granted Jun 11, 2019·0 cites·20 claims
- 2234US2008180129A1Fpga architecture with threshold voltage compensation and reduced leakageACTEL CORP·Filed 2007·Application pending·0 cites
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