Inventor · disambiguated record
Sandip Kundu
Also filed as: KUNDU SANDIP
13 granted patents·3 pending applications·272 citations·filing 1992–2014
92Inventor score
Top patents by PatentIndex Score
16 records- 0192US6938225B2Scan design for double-edge-triggered flip-flopsINTEL CORP·Filed 2002·Granted Aug 30, 2005·63 cites·11 claims
- 0290US6510398B1Constrained signature-based testINTEL CORP·Filed 2000·Granted Jan 21, 2003·68 cites·31 claims
- 0379US5796751ATechnique for sorting high frequency integrated circuitsIBM·Filed 1996·Granted Aug 18, 1998·45 cites·12 claims
- 0473US9520877B2Apparatus and method for detecting or repairing minimum delay errorsINTEL CORP·Filed 2014·Granted Dec 13, 2016·3 cites·16 claims
- 0572US7197721B2Weight compression/decompression systemINTEL CORP·Filed 2002·Granted Mar 27, 2007·16 cites·18 claims
- 0664US6715091B1System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operationINTEL CORP·Filed 2000·Granted Mar 30, 2004·11 cites·23 claims
- 0759US7096397B2Dft technique for avoiding contention/conflict in logic built-in self-testINTEL CORP·Filed 2001·Granted Aug 22, 2006·12 cites·29 claims
- 0857US5629858ACMOS transistor network to gate level model extractor for simulation, verification and test generationIBM·Filed 1995·Granted May 13, 1997·21 cites·2 claims
- 0953US6973422B1Method and apparatus for modeling and circuits with asynchronous behaviorINTEL CORP·Filed 2000·Granted Dec 6, 2005·4 cites·18 claims
- 1049US7036063B2Generalized fault model for defects and circuit marginalitiesINTEL CORP·Filed 2002·Granted Apr 25, 2006·1 cites·24 claims
- 1146US6912701B2Method and apparatus for power supply noise modeling and test pattern developmentINTEL CORP·Filed 2002·Granted Jun 28, 2005·3 cites·25 claims
- 1246US5297151AAdjustable weighted random test pattern generator for logic circuitsIBM·Filed 1992·Granted Mar 22, 1994·19 cites·16 claims
- 1341US2003188273A1Simulation-based technique for contention avoidance in automatic test pattern generationINTEL CORP·Filed 2002·Application pending·0 cites
- 1436US5793777ASystem and method for testing internal nodes of an integrated circuit at any predetermined machine cycleIBM·Filed 1996·Granted Aug 11, 1998·6 cites·10 claims
- 1531US2004205436A1Generalized fault model for defects and circuit marginalitiesFiled 2004·Application pending·0 cites
- 1630US2006052075A1Testing integrated circuits using high bandwidth wireless technologyGALIVANCHE RAJESHWAR·Filed 2004·Application pending·0 cites
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