Inventor · disambiguated record
Luiz Andre Barroso
Also filed as: BARROSO LUIZ A · BARROSO LUIZ ANDRE
35 granted patents·1,678 citations·filing 2001–2019
98Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO17GOOGLE INC8WEBER WOLF-DIETRICH6GOOGLE LLC3CARLSON ANDREW B1
Top patents by PatentIndex Score
35 records- 0199US9250999B1Non-volatile random access memory in computer primary memoryGOOGLE INC·Filed 2013·Granted Feb 2, 2016·184 cites·25 claims
- 0298US8700929B1Load control in a data centerWEBER WOLF-DIETRICH·Filed 2008·Granted Apr 15, 2014·82 cites·31 claims
- 0398US8595515B1Powering a data centerWEBER WOLF-DIETRICH·Filed 2008·Granted Nov 26, 2013·89 cites·35 claims
- 0498US6668308B2Scalable architecture based on single-chip multiprocessingHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 23, 2003·223 cites·4 claims
- 0597US9946815B1Computer and data center load determinationGOOGLE INC·Filed 2013·Granted Apr 17, 2018·30 cites·17 claims
- 0697US8601287B1Computer and data center load determinationWEBER WOLF-DIETRICH·Filed 2008·Granted Dec 3, 2013·52 cites·24 claims
- 0796US8621248B1Load control in a data centerWEBER WOLF-DIETRICH·Filed 2011·Granted Dec 31, 2013·24 cites·14 claims
- 0896US6725334B2Method and system for exclusive two-level caching in a chip-multiprocessorHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Apr 20, 2004·118 cites·18 claims
- 0995US8949646B1Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usageWEBER WOLF-DIETRICH·Filed 2008·Granted Feb 3, 2015·27 cites·23 claims
- 1095US6988170B2Scalable architecture based on single-chip multiprocessingHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jan 17, 2006·97 cites·29 claims
- 1195US6697919B2System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 24, 2004·108 cites·3 claims
- 1294US8645722B1Computer and data center load determinationWEBER WOLF-DIETRICH·Filed 2011·Granted Feb 4, 2014·17 cites·19 claims
- 1394US6622217B2Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Sep 16, 2003·114 cites·16 claims
- 1493US6675265B2Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participantsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 6, 2004·93 cites·14 claims
- 1592US9563216B1Managing power between data center loadsGOOGLE INC·Filed 2013·Granted Feb 7, 2017·19 cites·24 claims
- 1692US6636949B2System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessingHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 21, 2003·80 cites·41 claims
- 1789US10558768B1Computer and data center load determinationGOOGLE LLC·Filed 2018·Granted Feb 11, 2020·3 cites·20 claims
- 1889US6725343B2System and method for generating cache coherence directory entries and error correction codes in a multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Apr 20, 2004·61 cites·52 claims
- 1989US6640287B2Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requestsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 28, 2003·60 cites·41 claims
- 2085US6751720B2Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchyHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jun 15, 2004·42 cites·15 claims
- 2183US9384036B1Low latency thread context cachingGOOGLE INC·Filed 2013·Granted Jul 5, 2016·6 cites·20 claims
- 2282US11017130B1Data center designGOOGLE LLC·Filed 2019·Granted May 25, 2021·1 cites·20 claims
- 2382US10339227B1Data center designCARLSON ANDREW B·Filed 2008·Granted Jul 2, 2019·6 cites·28 claims
- 2482US7934131B1Server farm diagnostic and status systemGOOGLE INC·Filed 2009·Granted Apr 26, 2011·14 cites·18 claims
- 2580US6748498B2Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vectorHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jun 8, 2004·31 cites·49 claims
- 2676US9779058B2Modulating processsor core operationsGOOGLE INC·Filed 2015·Granted Oct 3, 2017·2 cites·20 claims
- 2776US6751710B2Scalable multiprocessor system and cache coherence methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 15, 2004·23 cites·54 claims
- 2872US6622218B2Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 16, 2003·18 cites·60 claims
- 2970US10127076B1Low latency thread context cachingGOOGLE LLC·Filed 2016·Granted Nov 13, 2018·1 cites·17 claims
- 3069US7389389B2System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jun 17, 2008·12 cites·17 claims
- 3169US6738868B2System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodesHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted May 18, 2004·14 cites·37 claims
- 3268US7386616B1System and method for providing load balanced processingGOOGLE INC·Filed 2003·Granted Jun 10, 2008·12 cites·14 claims
- 3366US6925537B2Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participantsHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 2, 2005·11 cites·6 claims
- 3457US6912624B2Method and system for exclusive two-level caching in a chip-multiprocessorHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Jun 28, 2005·4 cites·8 claims
- 3550US9218310B2Shared input/output (I/O) unitGOOGLE INC·Filed 2013·Granted Dec 22, 2015·0 cites·20 claims
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