Inventor · disambiguated record
Subramanyam Sripada
Also filed as: SRIPADA SUBRAMANYAM
14 granted patents·1 pending application·62 citations·filing 2004–2023
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0183US7900165B2Determining a design attribute by estimation and by calibration of estimated valueSYNOPSYS INC·Filed 2007·Granted Mar 1, 2011·11 cites·18 claims
- 0276US8924906B2Determining a design attribute by estimation and by calibration of estimated valueSYNOPSYS INC·Filed 2013·Granted Dec 30, 2014·3 cites·20 claims
- 0375US8627262B2Automatic generation of merged mode constraints for electronic circuitsSRIPADA SUBRAMANYAM·Filed 2010·Granted Jan 7, 2014·5 cites·17 claims
- 0472US8555235B2Determining a design attribute by estimation and by calibration of estimated valueOH NAHMSUK·Filed 2011·Granted Oct 8, 2013·4 cites·20 claims
- 0572US8473886B2Parallel parasitic processing in static timing analysisSRIPADA SUBRAMANYAM·Filed 2010·Granted Jun 25, 2013·4 cites·20 claims
- 0671US8607186B2Automatic verification of merged mode constraints for electronic circuitsSRIPADA SUBRAMANYAM·Filed 2011·Granted Dec 10, 2013·4 cites·17 claims
- 0769US8701074B2Automatic reduction of modes of electronic circuits for timing analysisSRIPADA SUBRAMANYAM·Filed 2011·Granted Apr 15, 2014·3 cites·24 claims
- 0869US7739098B2System and method for providing distributed static timing analysis with merged resultsSYNOPSYS INC·Filed 2004·Granted Jun 15, 2010·21 cites·62 claims
- 0959US9489478B2Simplifying modes of an electronic circuit by reducing constraintsSYNOPSYS INC·Filed 2014·Granted Nov 8, 2016·2 cites·20 claims
- 1058US7523428B2Hierarchical signal integrity analysis using interface logic modelsSYNOPSYS INC·Filed 2007·Granted Apr 21, 2009·1 cites·4 claims
- 1155US7216317B2Hierarchical signal integrity analysis using interface logic modelsSYNOPSYS INC·Filed 2004·Granted May 8, 2007·4 cites·7 claims
- 1253US12406127B2Static timing analysis of multi-die three-dimensional integrated circuitsSYNOPSYS INC·Filed 2022·Granted Sep 2, 2025·0 cites·20 claims
- 1352US12488169B1Performing timing constraint equivalence checking on circuit designsSYNOPSYS INC·Filed 2022·Granted Dec 2, 2025·0 cites·20 claims
- 1451US2024249053A1Timing analysis in stacked diesSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 1542US10339258B2Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO)SYNOPSYS INC·Filed 2015·Granted Jul 2, 2019·0 cites·12 claims
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