Inventor · disambiguated record
Terry Borer
Also filed as: BORER TERRY · BORER TERRY P
23 granted patents·1 pending application·308 citations·filing 2002–2017
96Inventor score
Top patents by PatentIndex Score
24 records- 0195US7669157B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesALTERA CORP·Filed 2006·Granted Feb 23, 2010·28 cites·21 claims
- 0288US7594208B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2006·Granted Sep 22, 2009·18 cites·31 claims
- 0385US7370295B1Directed design space explorationALTERA CORP·Filed 2005·Granted May 6, 2008·14 cites·26 claims
- 0485US7254801B1Synthesis aware placement: a novel approach that combines knowledge of possible resynthesisALTERA CORP·Filed 2005·Granted Aug 7, 2007·15 cites·40 claims
- 0584US8370776B1Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flowALTERA CORP·Filed 2008·Granted Feb 5, 2013·14 cites·20 claims
- 0683US8589849B1Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesBORER TERRY·Filed 2007·Granted Nov 19, 2013·10 cites·30 claims
- 0783US6779169B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2002·Granted Aug 17, 2004·32 cites·24 claims
- 0882US7464362B1Method and apparatus for performing incremental compilationALTERA CORP·Filed 2006·Granted Dec 9, 2008·12 cites·17 claims
- 0979US7360190B1Method and apparatus for performing retiming on field programmable gate arraysALTERA CORP·Filed 2004·Granted Apr 15, 2008·25 cites·31 claims
- 1079US7257800B1Method and apparatus for performing logic replication in field programmable gate arraysALTERA CORP·Filed 2004·Granted Aug 14, 2007·28 cites·34 claims
- 1177US7181703B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2003·Granted Feb 20, 2007·22 cites·21 claims
- 1275US8250505B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2009·Granted Aug 21, 2012·5 cites·17 claims
- 1374US7290240B1Leveraging combinations of synthesis, placement and incremental optimizationsALTERA CORP·Filed 2004·Granted Oct 30, 2007·25 cites·37 claims
- 1474US7194720B1Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devicesALTERA CORP·Filed 2003·Granted Mar 20, 2007·19 cites·26 claims
- 1567US9754065B2Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesALTERA CORP·Filed 2013·Granted Sep 5, 2017·1 cites·20 claims
- 1667US7181717B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2004·Granted Feb 20, 2007·10 cites·16 claims
- 1766US8589838B1M/A for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2012·Granted Nov 19, 2013·1 cites·24 claims
- 1863US8037435B1Directed design space explorationALTERA CORP·Filed 2008·Granted Oct 11, 2011·2 cites·18 claims
- 1963US7594204B1Method and apparatus for performing layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2003·Granted Sep 22, 2009·8 cites·17 claims
- 2062US7197734B1Method and apparatus for designing systems using logic regionsALTERA CORP·Filed 2002·Granted Mar 27, 2007·12 cites·30 claims
- 2157US9122826B1Method and apparatus for performing compilation using multiple design flowsALTERA CORP·Filed 2013·Granted Sep 1, 2015·0 cites·24 claims
- 2257US7401314B1Method and apparatus for performing compound duplication of components on field programmable gate arraysALTERA CORP·Filed 2005·Granted Jul 15, 2008·1 cites·22 claims
- 2356US2017337318A1Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic DevicesALTERA CORP·Filed 2017·Application pending·0 cites
- 2451US7389489B1Techniques for editing circuit design files to be compatible with a new programmable ICALTERA CORP·Filed 2004·Granted Jun 17, 2008·6 cites·18 claims
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