Inventor · disambiguated record
Bryan Lloyd
Also filed as: LLOYD BRYAN · LLOYD BRYAN J · LLOYD BRYAN JAY
64 granted patents·6 pending applications·400 citations·filing 1998–2023
98Inventor score
Top patents by PatentIndex Score
70 records- 0197US11249757B1Handling and fusing load instructions in a processorIBM·Filed 2020·Granted Feb 15, 2022·6 cites·18 claims
- 0296US10977175B2Virtual cache tag renaming for synonym handlingIBM·Filed 2019·Granted Apr 13, 2021·15 cites·20 claims
- 0395US10324856B2Address translation for sending real address to memory subsystem in effective address based load-store unitIBM·Filed 2017·Granted Jun 18, 2019·14 cites·7 claims
- 0495US10310988B2Address translation for sending real address to memory subsystem in effective address based load-store unitIBM·Filed 2017·Granted Jun 4, 2019·13 cites·13 claims
- 0593US10963248B2Handling effective address synonyms in a load-store unit that operates without address translationIBM·Filed 2020·Granted Mar 30, 2021·3 cites·20 claims
- 0693US10417002B2Hazard detection of out-of-order execution of load and store instructions in processors without using real addressesIBM·Filed 2017·Granted Sep 17, 2019·9 cites·17 claims
- 0793US10394558B2Executing load-store operations without address translation hardware per load-store unit portIBM·Filed 2017·Granted Aug 27, 2019·8 cites·13 claims
- 0892US11755324B2Gather buffer management for unaligned and gather load operationsIBM·Filed 2021·Granted Sep 12, 2023·2 cites·19 claims
- 0992US10534616B2Load-hit-load detection in an out-of-order processorIBM·Filed 2017·Granted Jan 14, 2020·10 cites·19 claims
- 1092US7675876B2Transport demultiplexor with bit maskable filterIBM·Filed 2005·Granted Mar 9, 2010·16 cites·18 claims
- 1191US11650926B2Virtual cache synonym detection using alias tagsIBM·Filed 2021·Granted May 16, 2023·2 cites·20 claims
- 1290US11520585B2Prefetch store preallocation in an effective address-based cache directoryIBM·Filed 2021·Granted Dec 6, 2022·2 cites·19 claims
- 1390US10977047B2Hazard detection of out-of-order execution of load and store instructions in processors without using real addressesIBM·Filed 2019·Granted Apr 13, 2021·5 cites·17 claims
- 1487US7646768B2Re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexorIBM·Filed 2006·Granted Jan 12, 2010·16 cites·18 claims
- 1586US10481915B2Split store data queue design for an out-of-order processorIBM·Filed 2017·Granted Nov 19, 2019·4 cites·17 claims
- 1685US10628158B2Executing load-store operations without address translation hardware per load-store unit portIBM·Filed 2017·Granted Apr 21, 2020·3 cites·7 claims
- 1785US9389867B2Speculative finish of instruction execution in a processor coreIBM·Filed 2015·Granted Jul 12, 2016·4 cites·6 claims
- 1885US7050113B2Digital video data scaler and methodIBM·Filed 2002·Granted May 23, 2006·29 cites·24 claims
- 1984US11119945B1Context tracking for multiple virtualization layers in a virtually tagged cacheIBM·Filed 2020·Granted Sep 14, 2021·2 cites·20 claims
- 2083US6731657B1Multiformat transport stream demultiplexorIBM·Filed 2000·Granted May 4, 2004·23 cites·20 claims
- 2182US11061810B2Virtual cache mechanism for program break point register exception handlingIBM·Filed 2019·Granted Jul 13, 2021·3 cites·18 claims
- 2282US10606591B2Handling effective address synonyms in a load-store unit that operates without address translationIBM·Filed 2017·Granted Mar 31, 2020·2 cites·13 claims
- 2382US10606592B2Handling effective address synonyms in a load-store unit that operates without address translationIBM·Filed 2017·Granted Mar 31, 2020·2 cites·7 claims
- 2482US7024685B1Transport demultiplexor with bit maskable filterIBM·Filed 2000·Granted Apr 4, 2006·21 cites·9 claims
- 2581US6317164B1System for creating multiple scaled videos from encoded video sourcesIBM·Filed 1999·Granted Nov 13, 2001·68 cites·15 claims
- 2680US11645208B2Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffersIBM·Filed 2021·Granted May 9, 2023·1 cites·14 claims
- 2779US11243773B1Area and power efficient mechanism to wakeup store-dependent loads according to store drain mergesIBM·Filed 2020·Granted Feb 8, 2022·1 cites·20 claims
- 2879US10572256B2Handling effective address synonyms in a load-store unit that operates without address translationIBM·Filed 2017·Granted Feb 25, 2020·2 cites·13 claims
- 2979US9384002B2Speculative finish of instruction execution in a processor coreIBM·Filed 2012·Granted Jul 5, 2016·4 cites·8 claims
- 3079US9086987B2Detection of conflicts between transactions and page shootdownsIBM·Filed 2012·Granted Jul 21, 2015·5 cites·17 claims
- 3177US10579387B2Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processorIBM·Filed 2017·Granted Mar 3, 2020·2 cites·17 claims
- 3277US6996101B2Re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexorIBM·Filed 2000·Granted Feb 7, 2006·23 cites·49 claims
- 3375US7028095B1Block-based negative filtering of MPEG-2 compliant table sectionsIBM·Filed 2000·Granted Apr 11, 2006·13 cites·14 claims
- 3474US6642934B2Color mapped and direct color OSD region processor with support for 4:2:2 profile decode functionIBM·Filed 2002·Granted Nov 4, 2003·10 cites·32 claims
- 3573US6542162B1Color mapped and direct color OSD region processor with support for 4:2:2 profile decode functionIBM·Filed 1998·Granted Apr 1, 2003·34 cites·14 claims
- 3670US12411688B2Gather buffer management for unaligned and gather load operationsIBM·Filed 2023·Granted Sep 9, 2025·0 cites·18 claims
- 3766US6944154B2System and method for remultiplexing of a filtered transport stream with new content in real-timeIBM·Filed 2000·Granted Sep 13, 2005·11 cites·18 claims
- 3866US6831931B2System and method for remultiplexing of a filtered transport streamIBM·Filed 2000·Granted Dec 14, 2004·7 cites·25 claims
- 3965US11500774B2Virtual cache tag renaming for synonym handlingIBM·Filed 2021·Granted Nov 15, 2022·0 cites·20 claims
- 4064US10776113B2Executing load-store operations without address translation hardware per load-store unit portIBM·Filed 2019·Granted Sep 15, 2020·0 cites·15 claims
- 4159US11687337B2Processor overriding of a false load-hit-store detectionIBM·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 4259US11321088B2Tracking load and store instructions and addresses in an out-of-order processorIBM·Filed 2020·Granted May 3, 2022·0 cites·25 claims
- 4358US11314510B2Tracking load and store instructions and addresses in an out-of-order processorIBM·Filed 2020·Granted Apr 26, 2022·0 cites·25 claims
- 4458US11086787B2Virtual cache synonym detection using alias tagsIBM·Filed 2019·Granted Aug 10, 2021·0 cites·20 claims
- 4558US10606590B2Effective address based load store unit in out of order processorsIBM·Filed 2017·Granted Mar 31, 2020·0 cites·13 claims
- 4658US10606593B2Effective address based load store unit in out of order processorsIBM·Filed 2017·Granted Mar 31, 2020·0 cites·7 claims
- 4758US10572257B2Handling effective address synonyms in a load-store unit that operates without address translationIBM·Filed 2017·Granted Feb 25, 2020·0 cites·7 claims
- 4857US11775337B2Prioritization of threads in a simultaneous multithreading processor coreIBM·Filed 2021·Granted Oct 3, 2023·0 cites·17 claims
- 4957US11537402B1Execution elision of intermediate instruction by processorIBM·Filed 2021·Granted Dec 27, 2022·0 cites·20 claims
- 5057US10664275B2Speeding up younger store instruction execution after a sync instructionIBM·Filed 2018·Granted May 26, 2020·0 cites·21 claims
Showing the top 50 of 70 patent records by PatentIndex Score.
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