Inventor · disambiguated record
Kent Hewitt
Also filed as: HEWITT KENT · HEWITT KENT D
18 granted patents·2 pending applications·442 citations·filing 1993–2019
95Inventor score
Top patents by PatentIndex Score
20 records- 0194US5488711ASerial EEPROM device and associated method for reducing data load time using a page mode write cacheMICROCHIP TECH INC·Filed 1993·Granted Jan 30, 1996·137 cites·5 claims
- 0290US5363334AWrite protection security for memory deviceMICROCHIP TECH INC·Filed 1993·Granted Nov 8, 1994·81 cites·17 claims
- 0382US5367484AProgrammable high endurance block for EEPROM deviceMICROCHIP TECH INC·Filed 1993·Granted Nov 22, 1994·60 cites·12 claims
- 0479US6222761B1Method for minimizing program disturb in a memory cellMICROCHIP TECH INC·Filed 2000·Granted Apr 24, 2001·25 cites·16 claims
- 0573US7466591B2Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuitsMICROCHIP TECH INC·Filed 2006·Granted Dec 16, 2008·6 cites·6 claims
- 0672US9455037B2EEPROM memory cell with low voltage read path and high voltage erase/write pathMICROCHIP TECH INC·Filed 2014·Granted Sep 27, 2016·3 cites·26 claims
- 0769US6236595B1Programming method for a memory cellMICROCHIP TECH INC·Filed 2000·Granted May 22, 2001·19 cites·13 claims
- 0867US6504191B2Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method thereforMICROCHIP TECH INC·Filed 2001·Granted Jan 7, 2003·11 cites·13 claims
- 0959US7817474B2Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuitsMICROCHIP TECH INC·Filed 2008·Granted Oct 19, 2010·3 cites·19 claims
- 1057US6300183B1Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method thereforMICROCHIP TECH INC·Filed 1999·Granted Oct 9, 2001·14 cites·6 claims
- 1155US8094503B2Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuitsSHIELDS JEFFREY A·Filed 2010·Granted Jan 10, 2012·2 cites·9 claims
- 1253US10910058B2Shared source line memory architecture for flash cell byte-alterable high endurance data memoryMICROCHIP TECH INC·Filed 2019·Granted Feb 2, 2021·1 cites·20 claims
- 1351US5675534AMethod and apparatus for preventing unauthorized access to nonvolatile memory in electronic encoders having a voltage level detection circuitMICROCHIP TECH INC·Filed 1996·Granted Oct 7, 1997·13 cites·6 claims
- 1447US5675622AMethod and apparatus for electronic encoding and decodingMICROCHIP TECH INC·Filed 1996·Granted Oct 7, 1997·36 cites·5 claims
- 1543US6150864ATime delay circuit which is voltage independentFiled 1998·Granted Nov 21, 2000·7 cites·12 claims
- 1642US5764099AIntegrated voltage regulating circuit useful in high voltage electronic encodersMICROCHIP TECH INC·Filed 1996·Granted Jun 9, 1998·17 cites·4 claims
- 1740US5604701AInitializing a read pipeline of a non-volatile sequential memory deviceMICROCHIP TECH INC·Filed 1995·Granted Feb 18, 1997·7 cites·12 claims
- 1833US2007140008A1Independently programmable memory segments within an NMOS electrically erasable programmable read only memory array achieved by P-well separation and method thereforMICROCHIP TECH INC·Filed 2005·Application pending·0 cites
- 1933US2002006059A1Method for minimizing program disturb in a memory cellFiled 2001·Application pending·0 cites
- 2025US9343147B2Resistive random access memory (ReRAM) and conductive bridging random access memory (CBRAM) cross coupled fuse and read method and systemMICROCHIP TECH INC·Filed 2014·Granted May 17, 2016·0 cites·25 claims
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