Inventor · disambiguated record
Robert Schell
Also filed as: SCHELL ROBERT · SCHELL ROBERT C
9 granted patents·2 pending applications·36 citations·filing 2011–2025
83Inventor score
Top patents by PatentIndex Score
11 records- 0191US8760209B2Apparatus and methods for quadrature clock signal generationANALOG DEVICES INC·Filed 2012·Granted Jun 24, 2014·15 cites·21 claims
- 0287US10177897B2Method and system for synchronizing and interleaving separate sampler groupsANALOG DEVICES INC·Filed 2016·Granted Jan 8, 2019·7 cites·20 claims
- 0387US8754678B1Apparatus and methods for invertible sine-shaping for phase interpolationANALOG DEVICES INC·Filed 2013·Granted Jun 17, 2014·10 cites·21 claims
- 0478US2025370498A1Synchronization of multiple clock dividers by using lower-frequency clocks and slipping cyclesAVAGO TECH INT SALES PTE LID·Filed 2025·Application pending·0 cites
- 0576US10033555B2Equalizer circuit optimization using coarse frequency detectionANALOG DEVICES INC·Filed 2016·Granted Jul 24, 2018·3 cites·20 claims
- 0670US12326752B2Synchronization of multiple clock dividers by using lower-frequency clocks and slipping cyclesAVAGO TECH INT SALES PTE LID·Filed 2023·Granted Jun 10, 2025·0 cites·20 claims
- 0755US11509338B2Nested feedback for offset cancellation in a wireline receiverANALOG DEVICES INC·Filed 2021·Granted Nov 22, 2022·0 cites·20 claims
- 0853US11444746B1Phasing detection of asynchronous dividersANALOG DEVICES INC·Filed 2021·Granted Sep 13, 2022·0 cites·20 claims
- 0952US12407488B2Quadrature divider error correctionAVAGO TECH INT SALES PTE LID·Filed 2023·Granted Sep 2, 2025·0 cites·17 claims
- 1045US8836549B2Use of logic circuit embedded into comparator for foreground offset cancellationSCHELL ROBERT·Filed 2011·Granted Sep 16, 2014·1 cites·22 claims
- 1143US2015288545A1Apparatus and methods for continuous-time equalizationANALOG DEVICES INC·Filed 2014·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →