Inventor · disambiguated record
Robert A. Cordes
Also filed as: CORDES ROBERT A · CORDES ROBERT ALLEN
28 granted patents·5 pending applications·217 citations·filing 2007–2023
95Inventor score
Top patents by PatentIndex Score
33 records- 0197US8108655B2Selecting fixed-point instructions to issue on load-store unitABERNATHY CHRISTOPHER MICHAEL·Filed 2009·Granted Jan 31, 2012·148 cites·20 claims
- 0291US10042770B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Aug 7, 2018·6 cites·7 claims
- 0391US10037229B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Jul 31, 2018·6 cites·13 claims
- 0491US9934033B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 3, 2018·8 cites·11 claims
- 0589US9940133B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 10, 2018·6 cites·6 claims
- 0689US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 0783US9798549B1Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2016·Granted Oct 24, 2017·3 cites·13 claims
- 0882US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 0981US10133576B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Granted Nov 20, 2018·2 cites·18 claims
- 1080US12061909B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2023·Granted Aug 13, 2024·0 cites·21 claims
- 1179US11243773B1Area and power efficient mechanism to wakeup store-dependent loads according to store drain mergesIBM·Filed 2020·Granted Feb 8, 2022·1 cites·20 claims
- 1279US10409598B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Sep 10, 2019·1 cites·5 claims
- 1379US8489863B2Processor including age tracking of issue queue instructionsBISHOP JAMES WILSON·Filed 2012·Granted Jul 16, 2013·5 cites·7 claims
- 1475US8127116B2Dependency matrix with reduced area and power consumptionISLAM SAIFUL·Filed 2009·Granted Feb 28, 2012·10 cites·18 claims
- 1574US11734010B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2021·Granted Aug 22, 2023·0 cites·21 claims
- 1674US10067763B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2015·Granted Sep 4, 2018·1 cites·9 claims
- 1768US10884742B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Jan 5, 2021·0 cites·9 claims
- 1867US10831481B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·14 claims
- 1964US11150907B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2018·Granted Oct 19, 2021·0 cites·19 claims
- 2064US10496406B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Dec 3, 2019·0 cites·9 claims
- 2163US10268518B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 23, 2019·0 cites·13 claims
- 2263US10255107B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 9, 2019·0 cites·7 claims
- 2356US10169046B2Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2017·Granted Jan 1, 2019·0 cites·12 claims
- 2456US2016202988A1Parallel slice processing method using a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Application pending·0 cites
- 2555US2025130947A1Clear prefetch stream on detection of pipeline flushIBM·Filed 2023·Application pending·0 cites
- 2654US11379241B2Handling oversize store to load forwarding in a processorIBM·Filed 2020·Granted Jul 5, 2022·0 cites·19 claims
- 2754US11263151B2Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operationsIBM·Filed 2020·Granted Mar 1, 2022·0 cites·20 claims
- 2852US11520704B1Writing store data of multiple store operations into a cache line in a single cycleIBM·Filed 2021·Granted Dec 6, 2022·0 cites·20 claims
- 2948US10223266B2Extended store forwarding for store misses without cache allocateIBM·Filed 2016·Granted Mar 5, 2019·0 cites·20 claims
- 3045US10761854B2Preventing hazard flushes in an instruction sequencing unit of a multi-slice processorIBM·Filed 2016·Granted Sep 1, 2020·0 cites·17 claims
- 3145US2009141682A1Method and apparatus to control audio switch during call handoffMOTOROLA INC·Filed 2007·Application pending·0 cites
- 3244US2022019436A1Fusion of microprocessor store instructionsIBM·Filed 2020·Application pending·0 cites
- 3343US2019391815A1Instruction age matrix and logic for queues in a processorIBM·Filed 2018·Application pending·0 cites
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