Inventor · disambiguated record
Denis M. Khartikov
Also filed as: KHARTIKOV DENIS · KHARTIKOV DENIS M
9 granted patents·2 pending applications·34 citations·filing 2009–2018
83Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0192US10642744B2Memory type which is cacheable yet inaccessible by speculative instructionsNVIDIA CORP·Filed 2018·Granted May 5, 2020·21 cites·24 claims
- 0278US10409763B2Apparatus and method for efficiently implementing a processor pipelineINTEL CORP·Filed 2014·Granted Sep 10, 2019·6 cites·8 claims
- 0374US9612840B2Method and apparatus for implementing a dynamic out-of-order processor pipelineINTEL CORP·Filed 2014·Granted Apr 4, 2017·3 cites·26 claims
- 0470US10338927B2Method and apparatus for implementing a dynamic out-of-order processor pipelineINTEL CORP·Filed 2017·Granted Jul 2, 2019·1 cites·27 claims
- 0562US9256497B2Checkpoints associated with an out of order architectureKHARTIKOV DENIS M·Filed 2014·Granted Feb 9, 2016·2 cites·23 claims
- 0660US9823925B2Instruction and logic for a logical move in an out-of-order processorINTEL CORP·Filed 2014·Granted Nov 21, 2017·1 cites·20 claims
- 0751US10061587B2Instruction and logic for bulk register reclamationINTEL CORP·Filed 2014·Granted Aug 28, 2018·0 cites·20 claims
- 0848US9342303B2Modified execution using context sensitive auxiliary codeINTEL CORP·Filed 2013·Granted May 17, 2016·0 cites·23 claims
- 0945US2010274972A1Systems, methods, and apparatuses for parallel computingBABAYAN BORIS·Filed 2009·Application pending·0 cites
- 1044US9569212B2Instruction and logic for a memory ordering bufferKELM JOHN H·Filed 2014·Granted Feb 14, 2017·0 cites·20 claims
- 1139US2015277914A1Lock elision with binary translation based processorsKELM JOHN H·Filed 2014·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →