Inventor · disambiguated record
Hang T. Nguyen
Also filed as: NGUYEN HANG · NGUYEN HANG T
56 granted patents·12 pending applications·1,102 citations·filing 1987–2020
99Inventor score
Top patents by PatentIndex Score
68 records- 0195US6615366B1Microprocessor with dual execution core operable in high reliability modeINTEL CORP·Filed 1999·Granted Sep 2, 2003·292 cites·24 claims
- 0294US8943334B2Providing per core voltage and frequency controlKUMAR PANKAJ·Filed 2010·Granted Jan 27, 2015·29 cites·15 claims
- 0392US5325921AMethod of propagating a hydraulic fracture using fluid loss control particulatesBAKER HUGHES INC·Filed 1992·Granted Jul 5, 1994·139 cites·28 claims
- 0491US7406553B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·18 cites·20 claims
- 0591US7055060B2On-die mechanism for high-reliability processorINTEL CORP·Filed 2002·Granted May 30, 2006·85 cites·16 claims
- 0689US9032226B2Providing per core voltage and frequency controlINTEL CORP·Filed 2013·Granted May 12, 2015·8 cites·19 claims
- 0789US8375184B2Mirroring data between redundant storage controllers of a storage systemINTEL CORP·Filed 2009·Granted Feb 12, 2013·24 cites·19 claims
- 0887US4755230AMethod of and composition for removing paraffin deposits from hydrocarbon transmission conduitsBAKER OIL TOOLS INC·Filed 1987·Granted Jul 5, 1988·81 cites·4 claims
- 0986US6543028B1Silent data corruption prevention due to instruction corruption by soft errorsINTEL CORP·Filed 2000·Granted Apr 1, 2003·50 cites·29 claims
- 1084US6651145B1Method and apparatus for scalable disambiguated coherence in shared storage hierarchiesINTEL CORP·Filed 2000·Granted Nov 18, 2003·35 cites·30 claims
- 1181US9037840B2Mechanism to provide workload and configuration-aware deterministic performance for microprocessorsVARMA ANKUSH·Filed 2012·Granted May 19, 2015·5 cites·20 claims
- 1281US6564332B1Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outletINTEL CORP·Filed 1998·Granted May 13, 2003·92 cites·17 claims
- 1380US10613620B2Providing per core voltage and frequency controlINTEL CORP·Filed 2018·Granted Apr 7, 2020·1 cites·20 claims
- 1480US10345884B2Mechanism to provide workload and configuration-aware deterministic performance for microprocessorsINTEL CORP·Filed 2016·Granted Jul 9, 2019·2 cites·20 claims
- 1578US6658621B1System and method for silent data corruption prevention due to next instruction pointer corruption by soft errorsINTEL CORP·Filed 2000·Granted Dec 2, 2003·27 cites·23 claims
- 1677US6954886B2Deterministic hardware reset for FRC machineINTEL CORP·Filed 2001·Granted Oct 11, 2005·22 cites·37 claims
- 1776US10936449B2Component redundancy systems, devices, and methodsINTEL CORP·Filed 2017·Granted Mar 2, 2021·2 cites·35 claims
- 1875US9983661B2Providing per core voltage and frequency controlINTEL CORP·Filed 2016·Granted May 29, 2018·1 cites·19 claims
- 1975US7428607B2Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2006·Granted Sep 23, 2008·5 cites·16 claims
- 2074US7634603B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2008·Granted Dec 15, 2009·4 cites·17 claims
- 2173US7464208B2Method and apparatus for shared resource management in a multiprocessing systemINTEL CORP·Filed 2006·Granted Dec 9, 2008·5 cites·18 claims
- 2273US7062613B2Methods and apparatus for cache interventionINTEL CORP·Filed 2005·Granted Jun 13, 2006·5 cites·38 claims
- 2372US7159077B2Direct processor cache access within a system having a coherent multi-processor protocolINTEL CORP·Filed 2004·Granted Jan 2, 2007·16 cites·30 claims
- 2471US7415633B2Method and apparatus for preventing and recovering from TLB corruption by soft errorINTEL CORP·Filed 2004·Granted Aug 19, 2008·13 cites·21 claims
- 2571US7100001B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Aug 29, 2006·16 cites·32 claims
- 2671US6684346B2Method and apparatus for machine check abort handling in a multiprocessing systemINTEL CORP·Filed 2000·Granted Jan 27, 2004·14 cites·30 claims
- 2769US7003632B2Method and apparatus for scalable disambiguated coherence in shared storage hierarchiesINTEL CORP·Filed 2003·Granted Feb 21, 2006·12 cites·20 claims
- 2868US7194671B2Mechanism handling race conditions in FRC-enabled processorsINTEL CORP·Filed 2001·Granted Mar 20, 2007·14 cites·20 claims
- 2966US7124224B2Method and apparatus for shared resource management in a multiprocessing systemINTEL CORP·Filed 2000·Granted Oct 17, 2006·10 cites·15 claims
- 3066US6983348B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Jan 3, 2006·10 cites·24 claims
- 3166US5446612ASelf loading suspension for hard disk drivesAREAL TECHNOLOGY INC·Filed 1994·Granted Aug 29, 1995·18 cites·2 claims
- 3264US7219176B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2002·Granted May 15, 2007·6 cites·23 claims
- 3363US7143220B2Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latenciesINTEL CORP·Filed 2004·Granted Nov 28, 2006·6 cites·30 claims
- 3462US9348387B2Providing per core voltage and frequency controlINTEL CORP·Filed 2014·Granted May 24, 2016·0 cites·18 claims
- 3561US9983659B2Providing per core voltage and frequency controlINTEL CORP·Filed 2015·Granted May 29, 2018·0 cites·20 claims
- 3661US9983660B2Providing per core voltage and frequency controlINTEL CORP·Filed 2015·Granted May 29, 2018·0 cites·19 claims
- 3761US9939884B2Providing per core voltage and frequency controlINTEL CORP·Filed 2015·Granted Apr 10, 2018·0 cites·15 claims
- 3860US7216252B1Method and apparatus for machine check abort handling in a multiprocessing systemINTEL CORP·Filed 2003·Granted May 8, 2007·6 cites·30 claims
- 3959US8533401B2Implementing direct access caches in coherent multiprocessorsEDIRISOORIYA SAMANTHA J·Filed 2002·Granted Sep 10, 2013·7 cites·4 claims
- 4059US7464227B2Method and apparatus for supporting opportunistic sharing in coherent multiprocessorsINTEL CORP·Filed 2002·Granted Dec 9, 2008·6 cites·27 claims
- 4156US9866498B2Technologies for network packet cache managementINTEL CORP·Filed 2014·Granted Jan 9, 2018·0 cites·25 claims
- 4255US7765349B1Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2008·Granted Jul 27, 2010·0 cites·19 claims
- 4354US7694080B2Method and apparatus for providing a low power mode for a processor while maintaining snoop throughputINTEL CORP·Filed 2004·Granted Apr 6, 2010·3 cites·14 claims
- 4453US9417681B2Mechanism to provide workload and configuration-aware deterministic performance for microprocessorsINTEL CORP·Filed 2015·Granted Aug 16, 2016·0 cites·20 claims
- 4552US9992299B2Technologies for network packet cache managementINTEL CORP·Filed 2017·Granted Jun 5, 2018·0 cites·28 claims
- 4652US7640387B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2008·Granted Dec 29, 2009·0 cites·20 claims
- 4752US7406552B2Systems and methods for early fixed latency subtractive decoding including speculative acknowledgingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·0 cites·17 claims
- 4850US7366845B2Pushing of clean data to one or more processors in a system having a coherency protocolINTEL CORP·Filed 2004·Granted Apr 29, 2008·1 cites·38 claims
- 4950US7360007B2System including a segmentable, shared busINTEL CORP·Filed 2002·Granted Apr 15, 2008·1 cites·12 claims
- 5050US7353317B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2004·Granted Apr 1, 2008·1 cites·25 claims
Showing the top 50 of 68 patent records by PatentIndex Score.
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