Inventor · disambiguated record
Sujat Jamil
Also filed as: JAMIL SUJAT
67 granted patents·11 pending applications·1,039 citations·filing 1998–2017
99Inventor score
Top patents by PatentIndex Score
78 records- 0197US9223709B1Thread-aware cache memory managementMARVELL INT LTD·Filed 2013·Granted Dec 29, 2015·49 cites·21 claims
- 0296US8918625B1Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparisonO'BLENESS R FRANK·Filed 2011·Granted Dec 23, 2014·59 cites·19 claims
- 0395US9934152B1Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cacheMARVELL INT LTD·Filed 2016·Granted Apr 3, 2018·24 cites·20 claims
- 0495US9026769B1Detecting and reissuing of loop instructions in reorder structureJAMIL SUJAT·Filed 2012·Granted May 5, 2015·43 cites·20 claims
- 0595US8990505B1Cache memory bank selectionJAMIL SUJAT·Filed 2008·Granted Mar 24, 2015·58 cites·34 claims
- 0692US9058272B1Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addressesMARVELL INT LTD·Filed 2013·Granted Jun 16, 2015·26 cites·17 claims
- 0791US7406553B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·18 cites·20 claims
- 0891US7055060B2On-die mechanism for high-reliability processorINTEL CORP·Filed 2002·Granted May 30, 2006·85 cites·16 claims
- 0990US8943273B1Method and apparatus for improving cache efficiencyJAMIL SUJAT·Filed 2009·Granted Jan 27, 2015·31 cites·20 claims
- 1088US8458404B1Programmable cache access protocol to optimize power consumption and performanceDELGROSS JOSEPH·Filed 2009·Granted Jun 4, 2013·24 cites·20 claims
- 1187US8135916B1Method and apparatus for hardware-configurable multi-policy coherence protocolO'BLENESS R FRANK·Filed 2009·Granted Mar 13, 2012·19 cites·11 claims
- 1286US9606800B1Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architectureMARVELL INT LTD·Filed 2013·Granted Mar 28, 2017·9 cites·20 claims
- 1386US7404043B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Jul 22, 2008·11 cites·16 claims
- 1486US6718494B1Method and apparatus for preventing and recovering from TLB corruption by soft errorINTEL CORP·Filed 2000·Granted Apr 6, 2004·43 cites·22 claims
- 1586US6543028B1Silent data corruption prevention due to instruction corruption by soft errorsINTEL CORP·Filed 2000·Granted Apr 1, 2003·50 cites·29 claims
- 1684US9842051B1Managing aliasing in a virtually indexed physically tagged cacheMARVELL INT LTD·Filed 2016·Granted Dec 12, 2017·4 cites·20 claims
- 1784US7917907B2Method and system for variable thread allocation and switching in a multithreaded processorQUALCOMM INC·Filed 2005·Granted Mar 29, 2011·14 cites·16 claims
- 1884US6651145B1Method and apparatus for scalable disambiguated coherence in shared storage hierarchiesINTEL CORP·Filed 2000·Granted Nov 18, 2003·35 cites·30 claims
- 1983US8806181B1Dynamic pipeline reconfiguration including changing a number of stagesO'BLENESS R FRANK·Filed 2009·Granted Aug 12, 2014·14 cites·12 claims
- 2083US7120755B2Transfer of cache lines on-chip between processing cores in a multi-core systemINTEL CORP·Filed 2002·Granted Oct 10, 2006·38 cites·13 claims
- 2181US9442735B1Method and apparatus for processing speculative, out-of-order memory access instructionsMARVELL INT LTD·Filed 2013·Granted Sep 13, 2016·6 cites·20 claims
- 2281US8631206B1Way-selecting translation lookaside bufferO'BLENESS R FRANK·Filed 2008·Granted Jan 14, 2014·11 cites·11 claims
- 2380US6240510B1System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructionsINTEL CORP·Filed 1998·Granted May 29, 2001·89 cites·32 claims
- 2478US6658621B1System and method for silent data corruption prevention due to next instruction pointer corruption by soft errorsINTEL CORP·Filed 2000·Granted Dec 2, 2003·27 cites·23 claims
- 2577US8296525B1Method and apparatus for data-less bus queryO'BLENESS FRANK·Filed 2009·Granted Oct 23, 2012·9 cites·20 claims
- 2675US7523295B2Processor and method of grouping and executing dependent instructions in a packetQUALCOMM INC·Filed 2005·Granted Apr 21, 2009·7 cites·22 claims
- 2775US7428607B2Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2006·Granted Sep 23, 2008·5 cites·16 claims
- 2875US6304960B1Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditionsINTEL CORP·Filed 1998·Granted Oct 16, 2001·70 cites·25 claims
- 2974US7634603B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2008·Granted Dec 15, 2009·4 cites·17 claims
- 3074US6775748B2Methods and apparatus for transferring cache block ownershipINTEL CORP·Filed 2002·Granted Aug 10, 2004·20 cites·31 claims
- 3173US7062613B2Methods and apparatus for cache interventionINTEL CORP·Filed 2005·Granted Jun 13, 2006·5 cites·38 claims
- 3272US8688919B1Method and apparatus for associating requests and responses with identification informationMARVELL INT LTD·Filed 2012·Granted Apr 1, 2014·2 cites·20 claims
- 3372US7159077B2Direct processor cache access within a system having a coherent multi-processor protocolINTEL CORP·Filed 2004·Granted Jan 2, 2007·16 cites·30 claims
- 3471US7415633B2Method and apparatus for preventing and recovering from TLB corruption by soft errorINTEL CORP·Filed 2004·Granted Aug 19, 2008·13 cites·21 claims
- 3571US7100001B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Aug 29, 2006·16 cites·32 claims
- 3669US7003632B2Method and apparatus for scalable disambiguated coherence in shared storage hierarchiesINTEL CORP·Filed 2003·Granted Feb 21, 2006·12 cites·20 claims
- 3768US7194671B2Mechanism handling race conditions in FRC-enabled processorsINTEL CORP·Filed 2001·Granted Mar 20, 2007·14 cites·20 claims
- 3866US6983348B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Jan 3, 2006·10 cites·24 claims
- 3965US9116742B1Systems and methods for reducing interrupt latencySCHUTTENBERG KIM·Filed 2012·Granted Aug 25, 2015·2 cites·20 claims
- 4064US7219176B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2002·Granted May 15, 2007·6 cites·23 claims
- 4163US7143220B2Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latenciesINTEL CORP·Filed 2004·Granted Nov 28, 2006·6 cites·30 claims
- 4262US7620778B2Low power microprocessor cache memory and method of operationQUALCOMM INC·Filed 2005·Granted Nov 17, 2009·5 cites·19 claims
- 4361US8195916B2Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing modeBASSETT PAUL DOUGLAS·Filed 2009·Granted Jun 5, 2012·3 cites·65 claims
- 4461US7290093B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2003·Granted Oct 30, 2007·5 cites·7 claims
- 4559US8533401B2Implementing direct access caches in coherent multiprocessorsEDIRISOORIYA SAMANTHA J·Filed 2002·Granted Sep 10, 2013·7 cites·4 claims
- 4659US7464227B2Method and apparatus for supporting opportunistic sharing in coherent multiprocessorsINTEL CORP·Filed 2002·Granted Dec 9, 2008·6 cites·27 claims
- 4756US9086976B1Method and apparatus for associating requests and responses with identification informationMARVELL INT LTD·Filed 2014·Granted Jul 21, 2015·0 cites·20 claims
- 4856US8099448B2Arithmetic logic and shifting device for use in a processorAHMED MUHAMMAD·Filed 2005·Granted Jan 17, 2012·1 cites·18 claims
- 4955US10230542B2Interconnected ring network in a multi-processor systemMARVELL WORLD TRADE LTD·Filed 2017·Granted Mar 12, 2019·0 cites·15 claims
- 5055US9454480B2Interconnected ring network in a multi-processor systemMARVELL WORLD TRADE LTD·Filed 2014·Granted Sep 27, 2016·0 cites·20 claims
Showing the top 50 of 78 patent records by PatentIndex Score.
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