Inventor · disambiguated record
Samantha J. Edirisooriya
Also filed as: EDIRISOORIYA SAMANTHA · EDIRISOORIYA SAMANTHA J · EDIRISOORIYA SAMANTHA J W
39 granted patents·14 pending applications·265 citations·filing 1998–2019
97Inventor score
Top patents by PatentIndex Score
53 records- 0191US7406553B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·18 cites·20 claims
- 0288US10241947B2Hardware-based virtual machine communicationINTEL CORP·Filed 2017·Granted Mar 26, 2019·6 cites·20 claims
- 0386US7404043B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Jul 22, 2008·11 cites·16 claims
- 0479US6247157B1Method of encoding data signals for storageINTEL CORP·Filed 1998·Granted Jun 12, 2001·81 cites·36 claims
- 0577US10810138B2Enhanced storage encryption with total memory encryption (TME) and multi-key total memory encryption (MKTME)INTEL CORP·Filed 2018·Granted Oct 20, 2020·4 cites·17 claims
- 0677US10127968B2Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh modeINTEL CORP·Filed 2015·Granted Nov 13, 2018·3 cites·20 claims
- 0775US7428607B2Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2006·Granted Sep 23, 2008·5 cites·16 claims
- 0874US9953001B2Method, apparatus, and system for plugin mechanism of computer extension busINTEL CORP·Filed 2016·Granted Apr 24, 2018·2 cites·22 claims
- 0974US7634603B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2008·Granted Dec 15, 2009·4 cites·17 claims
- 1074US6775748B2Methods and apparatus for transferring cache block ownershipINTEL CORP·Filed 2002·Granted Aug 10, 2004·20 cites·31 claims
- 1173US7343546B2Method and system for syndrome generation and data recoveryINTEL CORP·Filed 2004·Granted Mar 11, 2008·16 cites·23 claims
- 1273US7062613B2Methods and apparatus for cache interventionINTEL CORP·Filed 2005·Granted Jun 13, 2006·5 cites·38 claims
- 1372US7159077B2Direct processor cache access within a system having a coherent multi-processor protocolINTEL CORP·Filed 2004·Granted Jan 2, 2007·16 cites·30 claims
- 1471US7100001B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Aug 29, 2006·16 cites·32 claims
- 1568US8156406B2Method and system for syndrome generation and data recoveryEDIRISOORIYA SAMANTHA J·Filed 2008·Granted Apr 10, 2012·4 cites·19 claims
- 1666US6983348B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Jan 3, 2006·10 cites·24 claims
- 1764US7219176B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2002·Granted May 15, 2007·6 cites·23 claims
- 1863US7143220B2Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latenciesINTEL CORP·Filed 2004·Granted Nov 28, 2006·6 cites·30 claims
- 1961US7290093B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2003·Granted Oct 30, 2007·5 cites·7 claims
- 2060US10990546B2Hardware-based virtual machine communication supporting direct memory access data transferINTEL CORP·Filed 2019·Granted Apr 27, 2021·0 cites·20 claims
- 2159US8533401B2Implementing direct access caches in coherent multiprocessorsEDIRISOORIYA SAMANTHA J·Filed 2002·Granted Sep 10, 2013·7 cites·4 claims
- 2259US7464227B2Method and apparatus for supporting opportunistic sharing in coherent multiprocessorsINTEL CORP·Filed 2002·Granted Dec 9, 2008·6 cites·27 claims
- 2357US7447810B2Implementing bufferless Direct Memory Access (DMA) controllers using split transactionsINTEL CORP·Filed 2004·Granted Nov 4, 2008·4 cites·8 claims
- 2456US7330998B2Data integrity verificationINTEL CORP·Filed 2004·Granted Feb 12, 2008·4 cites·20 claims
- 2555US7765349B1Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2008·Granted Jul 27, 2010·0 cites·19 claims
- 2655US7698476B2Implementing bufferless direct memory access (DMA) controllers using split transactionsINTEL CORP·Filed 2008·Granted Apr 13, 2010·0 cites·20 claims
- 2754US7234028B2Power/performance optimized cache using memory write prevention through write snarfingINTEL CORP·Filed 2002·Granted Jun 19, 2007·3 cites·25 claims
- 2852US7640387B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2008·Granted Dec 29, 2009·0 cites·20 claims
- 2952US7406552B2Systems and methods for early fixed latency subtractive decoding including speculative acknowledgingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·0 cites·17 claims
- 3050US10679690B2Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh modeINTEL CORP·Filed 2018·Granted Jun 9, 2020·0 cites·19 claims
- 3150US7366845B2Pushing of clean data to one or more processors in a system having a coherency protocolINTEL CORP·Filed 2004·Granted Apr 29, 2008·1 cites·38 claims
- 3250US7360007B2System including a segmentable, shared busINTEL CORP·Filed 2002·Granted Apr 15, 2008·1 cites·12 claims
- 3350US7353317B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2004·Granted Apr 1, 2008·1 cites·25 claims
- 3449US10235302B2Invalidating reads for cache utilization in processorsINTEL CORP·Filed 2016·Granted Mar 19, 2019·0 cites·20 claims
- 3549US7487299B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Feb 3, 2009·0 cites·9 claims
- 3648US7966477B1Power optimized replay of blocked operations in a pipilined architectureMARVELL INT LTD·Filed 2010·Granted Jun 21, 2011·0 cites·14 claims
- 3748US7685379B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Mar 23, 2010·0 cites·12 claims
- 3846US7725683B2Apparatus and method for power optimized replay via selective recirculation of instructionsMARVELL INT LTD·Filed 2003·Granted May 25, 2010·0 cites·18 claims
- 3946US2016092123A1Memory write management in a computer systemKUMAR PANKAJ·Filed 2014·Application pending·0 cites
- 4046US2006112238A1Techniques for pushing data to a processor cacheJAMIL SUJAT·Filed 2004·Application pending·0 cites
- 4145US2005125582A1Methods and apparatus to dispatch interrupts in multi-processor systemsFiled 2003·Application pending·0 cites
- 4244US2006095679A1Method and apparatus for pushing data into a processor cacheEDIRISOORIYA SAMANTHA J·Filed 2004·Application pending·0 cites
- 4344US2006136619A1Data integrity processing and protection techniquesINTEL CORP·Filed 2004·Application pending·0 cites
- 4444US2006090016A1Mechanism to pull data into a processor cacheEDIRISOORIYA SAMANTHA J·Filed 2004·Application pending·0 cites
- 4543US2004111563A1Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processorsFiled 2002·Application pending·0 cites
- 4643US2004153611A1Methods and apparatus for detecting an address conflictFiled 2003·Application pending·0 cites
- 4743US2004015669A1Method, system, and apparatus for an efficient cache to support multiple configurationsFiled 2002·Application pending·0 cites
- 4843US2006294299A1Techniques to verify storage of informationINTEL CORP·Filed 2005·Application pending·0 cites
- 4942US2005289253A1Apparatus and method for a multi-function direct memory access coreEDIRISOORIYA SAMANTHA J·Filed 2004·Application pending·0 cites
- 5041US7757046B2Method and apparatus for optimizing line writes in cache coherent systemsINTEL CORP·Filed 2002·Granted Jul 13, 2010·0 cites·15 claims
Showing the top 50 of 53 patent records by PatentIndex Score.
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