Inventor · disambiguated record
Gerard M. Col
Also filed as: COL GERARD · COL GERARD M
73 granted patents·1 pending application·848 citations·filing 1997–2015
99Inventor score
Top patents by PatentIndex Score
74 records- 0192US6647489B1Compare branch instruction pairing within a single integer pipelineIP FIRST LLC·Filed 2000·Granted Nov 11, 2003·76 cites·29 claims
- 0290US8090931B2Microprocessor with fused store address/store data microinstructionCOL GERARD M·Filed 2008·Granted Jan 3, 2012·24 cites·12 claims
- 0389US7065632B1Method and apparatus for speculatively forwarding storehit data in a hierarchical mannerIP FIRST LLC·Filed 2000·Granted Jun 20, 2006·65 cites·15 claims
- 0487US9244686B2Microprocessor that translates conditional load/store instructions into variable number of microinstructionsHENRY G GLENN·Filed 2012·Granted Jan 26, 2016·10 cites·47 claims
- 0586US6526502B1Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcomeIP FIRST LLC·Filed 2000·Granted Feb 25, 2003·38 cites·31 claims
- 0685US7117347B2Processor including fallback branch prediction mechanism for far jump and far call instructionsIP FIRST LLC·Filed 2002·Granted Oct 3, 2006·42 cites·15 claims
- 0782US8074060B2Out-of-order execution microprocessor that selectively initiates instruction retirement earlyCOL GERARD M·Filed 2008·Granted Dec 6, 2011·13 cites·21 claims
- 0881US9501286B2Microprocessor with ALU integrated into load unitCOL GERARD M·Filed 2009·Granted Nov 22, 2016·9 cites·38 claims
- 0980US6338136B1Pairing of load-ALU-store with conditional branchIP FIRST LLC·Filed 1999·Granted Jan 8, 2002·89 cites·24 claims
- 1079US7937561B2Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitectureVIA TECH INC·Filed 2008·Granted May 3, 2011·9 cites·21 claims
- 1179US6629234B1Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instructionIP FIRST LLC·Filed 2000·Granted Sep 30, 2003·25 cites·12 claims
- 1278US6931517B1Pop-compare micro instruction for repeat string operationsIP FIRST LLC·Filed 2002·Granted Aug 16, 2005·25 cites·25 claims
- 1375US6108773AApparatus and method for branch target address calculation during instruction decodeIP FIRST LLC·Filed 1998·Granted Aug 22, 2000·71 cites·34 claims
- 1474US10114794B2Programmable load replay precluding mechanismVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Oct 30, 2018·3 cites·12 claims
- 1574US8069339B2Microprocessor with microinstruction-specifiable non-architectural condition code flag registerHENRY G GLENN·Filed 2009·Granted Nov 29, 2011·6 cites·22 claims
- 1672US6581150B1Apparatus and method for improved non-page fault loads and storesIP FIRST LLC·Filed 2000·Granted Jun 17, 2003·17 cites·30 claims
- 1771US6427207B1Result forwarding cacheI P FIRST L L C·Filed 2001·Granted Jul 30, 2002·14 cites·17 claims
- 1871US6189091B1Apparatus and method for speculatively updating global history and restoring same on branch misprediction detectionIP FIRST LLC·Filed 1998·Granted Feb 13, 2001·53 cites·22 claims
- 1970US6591343B1Predecode in parallel with TLB compareIP FIRST LLC·Filed 2000·Granted Jul 8, 2003·16 cites·16 claims
- 2068US9378019B2Conditional load instructions in an out-of-order execution microprocessorHENRY G GLENN·Filed 2012·Granted Jun 28, 2016·2 cites·39 claims
- 2168US7185182B2Pipelined microprocessor, apparatus, and method for generating early instruction resultsVIA TECH INC·Filed 2004·Granted Feb 27, 2007·13 cites·20 claims
- 2266US8880854B2Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment registerHOOKER RODNEY E·Filed 2009·Granted Nov 4, 2014·3 cites·14 claims
- 2366US7055022B1Paired load-branch operation for indirect near jumpsIP FIRST LLC·Filed 2002·Granted May 30, 2006·11 cites·16 claims
- 2465US10127046B2Mechanism to preclude uncacheable-dependent load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Nov 13, 2018·1 cites·12 claims
- 2565US6330657B1Pairing of micro instructions in the instruction queueIP FIRST LLC·Filed 1999·Granted Dec 11, 2001·43 cites·36 claims
- 2663US7058794B2Apparatus and method for masked move to and from flags register in a processorCOL GERARD M·Filed 2002·Granted Jun 6, 2006·9 cites·10 claims
- 2763US6349383B1System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for executionIP FIRST LLC·Filed 1998·Granted Feb 19, 2002·42 cites·24 claims
- 2862US9645822B2Conditional store instructions in an out-of-order execution microprocessorHENRY G GLENN·Filed 2012·Granted May 9, 2017·1 cites·43 claims
- 2962US9588769B2Processor that leapfrogs MOV instructionsVIA TECH INC·Filed 2014·Granted Mar 7, 2017·1 cites·20 claims
- 3062US9032189B2Efficient conditional ALU instruction in read-port limited register file microprocessorHENRY G GLENN·Filed 2011·Granted May 12, 2015·1 cites·34 claims
- 3160US8909908B2Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instructionHOOKER RODNEY E·Filed 2009·Granted Dec 9, 2014·2 cites·11 claims
- 3260US7039793B2Microprocessor apparatus and method for accelerating execution of repeat string instructionsIP FIRST LLC·Filed 2002·Granted May 2, 2006·7 cites·10 claims
- 3358US9703359B2Power saving mechanism to reduce load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Jul 11, 2017·0 cites·21 claims
- 3457US7100024B2Pipelined microprocessor, apparatus, and method for generating early status flagsVIA TECH INC·Filed 2004·Granted Aug 29, 2006·5 cites·80 claims
- 3556US7076639B2Apparatus and method for masked move to and from flags register in a processorIP FIRST LLC·Filed 2002·Granted Jul 11, 2006·4 cites·13 claims
- 3656US5887175AApparatus and method for managing interrupt delay on floating point errorINTEGRATED DEVICE TECH·Filed 1997·Granted Mar 23, 1999·30 cites·26 claims
- 3755US9952875B2Microprocessor with ALU integrated into store unitCOL GERARD M·Filed 2009·Granted Apr 24, 2018·0 cites·38 claims
- 3855US6725359B2Address stage logic for generating speculative address operand interim results of preceding instruction by arithmetic operations and configuringIP FIRST LLC·Filed 2003·Granted Apr 20, 2004·3 cites·10 claims
- 3954US10108430B2Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Oct 23, 2018·0 cites·13 claims
- 4053US9915998B2Power saving mechanism to reduce load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Mar 13, 2018·0 cites·21 claims
- 4152US9740271B2Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Aug 22, 2017·0 cites·21 claims
- 4252US9645827B2Mechanism to preclude load replays dependent on page walks in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted May 9, 2017·0 cites·21 claims
- 4352US7107438B2Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictionsVIA TECH INC·Filed 2004·Granted Sep 12, 2006·2 cites·94 claims
- 4451US8332618B2Out-of-order X86 microprocessor with fast shift-by-zero handlingCOL GERARD M·Filed 2009·Granted Dec 11, 2012·0 cites·24 claims
- 4551US6343359B1Result forwarding cacheIP FIRST LLC·Filed 1999·Granted Jan 29, 2002·20 cites·19 claims
- 4651US6209082B1Apparatus and method for optimizing execution of push all/pop all instructionsIP FIRST LLC·Filed 1998·Granted Mar 27, 2001·25 cites·21 claims
- 4750US10209996B2Apparatus and method for programmable load replay preclusionVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Feb 19, 2019·0 cites·12 claims
- 4850US10146546B2Load replay precluding mechanismVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Dec 4, 2018·0 cites·12 claims
- 4950US10146547B2Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Dec 4, 2018·0 cites·12 claims
- 5050US10133579B2Mechanism to preclude uncacheable-dependent load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Nov 20, 2018·0 cites·12 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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