Inventor · disambiguated record
Ugonna Echeruo
Also filed as: ECHERUO UGONNA · ECHERUO UGONNA C
6 granted patents·3 pending applications·16 citations·filing 2004–2021
74Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0166US7380169B2Converting merge buffer system-kill errors to process-kill errorsINTEL CORP·Filed 2004·Granted May 27, 2008·12 cites·20 claims
- 0259US11256626B2Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristicsINTEL CORP·Filed 2020·Granted Feb 22, 2022·0 cites·22 claims
- 0358US10719317B2Hardware apparatuses and methods relating to elemental register accessesINTEL CORP·Filed 2018·Granted Jul 21, 2020·0 cites·24 claims
- 0457US9996347B2Hardware apparatuses and methods relating to elemental register accessesINTEL CORP·Filed 2014·Granted Jun 12, 2018·0 cites·24 claims
- 0555US7607048B2Method and apparatus for protecting TLB's VPN from soft errorsINTEL CORP·Filed 2004·Granted Oct 20, 2009·4 cites·14 claims
- 0652US10621099B2Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristicsINTEL CORP·Filed 2018·Granted Apr 14, 2020·0 cites·25 claims
- 0745US2024241778A1In-system mitigation of uncorrectable errors based on confidence factors, based on fault-aware analysisINTEL CORP·Filed 2021·Application pending·0 cites
- 0844US2006026371A1Method and apparatus for implementing memory order models with order vectorsCHRYSOS GEORGE Z·Filed 2004·Application pending·0 cites
- 0944US2023091205A1Memory side prefetch architecture for improved memory bandwidthINTEL CORP·Filed 2021·Application pending·0 cites
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