Inventor · disambiguated record
Ivan L. Wemple
Also filed as: WEMPLE IVAN · WEMPLE IVAN L
23 granted patents·1 pending application·438 citations·filing 1989–2013
96Inventor score
Top patents by PatentIndex Score
24 records- 0195US7475366B2Integrated circuit design closure method for selective voltage binningIBM·Filed 2006·Granted Jan 6, 2009·53 cites·14 claims
- 0292US7000214B2Method for designing an integrated circuit having multiple voltage domainsIBM·Filed 2003·Granted Feb 14, 2006·79 cites·20 claims
- 0391US7142991B2Voltage dependent parameter analysisIBM·Filed 2005·Granted Nov 28, 2006·28 cites·28 claims
- 0490US6631502B2Method of analyzing integrated circuit power distribution in chips containing voltage islandsIBM·Filed 2002·Granted Oct 7, 2003·88 cites·16 claims
- 0589US6523154B2Method for supply voltage drop analysis during placement phase of chip designIBM·Filed 2000·Granted Feb 18, 2003·63 cites·15 claims
- 0686US7404163B2Static timing slacks analysis and modificationIBM·Filed 2006·Granted Jul 22, 2008·16 cites·17 claims
- 0780US8988140B2Real-time adaptive voltage control of logic blocksIBM·Filed 2013·Granted Mar 24, 2015·5 cites·19 claims
- 0879US6832361B2System and method for analyzing power distribution using static timing analysisIBM·Filed 2001·Granted Dec 14, 2004·27 cites·34 claims
- 0978US8302063B2Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compressionBICKFORD JEANNE P·Filed 2010·Granted Oct 30, 2012·6 cites·20 claims
- 1074US6948146B2Simplified tiling pattern methodIBM·Filed 2003·Granted Sep 20, 2005·20 cites·22 claims
- 1172US7441213B2Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereofIBM·Filed 2006·Granted Oct 21, 2008·7 cites·12 claims
- 1270US8015526B2Static timing slacks analysis and modificationIBM·Filed 2008·Granted Sep 6, 2011·4 cites·17 claims
- 1362US7257788B2Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuitsIBM·Filed 2004·Granted Aug 14, 2007·7 cites·18 claims
- 1460US7454305B2Method and apparatus for storing circuit calibration informationIBM·Filed 2005·Granted Nov 18, 2008·3 cites·12 claims
- 1560US6698008B2Row-based placement scoring and legalization measure for books with phase shift mask dependenciesIBM·Filed 2001·Granted Feb 24, 2004·5 cites·20 claims
- 1659US7961932B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2007·Granted Jun 14, 2011·1 cites·4 claims
- 1755US8438520B2Early decoupling capacitor optimization method for hierarchical circuit designCARLSEN KURT A·Filed 2011·Granted May 7, 2013·1 cites·24 claims
- 1850US2007220468A1Method and Apparatus for Converting Globally Clock-Gated Circuits to Locally Clock-Gated CircuitsHAAR ALLEN P·Filed 2007·Application pending·0 cites
- 1948US5010018AMethod for forming Schottky photodiodesGEN ELECTRIC·Filed 1990·Granted Apr 23, 1991·14 cites·11 claims
- 2046US7289659B2Method and apparatus for manufacturing diamond shaped chipsIBM·Filed 2003·Granted Oct 30, 2007·2 cites·23 claims
- 2146US6963240B2Damping of LC ringing in IC (integrated circuit) power distribution systemsIBM·Filed 2003·Granted Nov 8, 2005·2 cites·14 claims
- 2245US6927616B2Integrated circuit and method for interfacing two voltage domains using a transformerIBM·Filed 2003·Granted Aug 9, 2005·2 cites·16 claims
- 2343US7669159B2IC tiling pattern method, IC so formed and analysis methodIBM·Filed 2005·Granted Feb 23, 2010·0 cites·12 claims
- 2435US4982246ASchottky photodiode with silicide layerGEN ELECTRIC·Filed 1989·Granted Jan 1, 1991·5 cites·8 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →