Inventor · disambiguated record
Chung Wai Leung
Also filed as: LEUNG CHUNG · LEUNG CHUNG W · LEUNG CHUNG WAI
31 granted patents·2 pending applications·822 citations·filing 1982–2009
97Inventor score
Files withMOSEL VITELIC INC8AT & T BELL LAB5AGERE SYST GUARDIAN CORP4AGERE SYSTEMS INC4LUCENT TECHNOLOGIES INC4
Top patents by PatentIndex Score
33 records- 0198US6355524B1Nonvolatile memory structures and fabrication methodsMOSEL VITELIC INC·Filed 2000·Granted Mar 12, 2002·193 cites·33 claims
- 0292US6191980B1Single-poly non-volatile memory cell having low-capacitance erase gateLUCENT TECHNOLOGIES INC·Filed 2000·Granted Feb 20, 2001·76 cites·22 claims
- 0388US6566196B1Sidewall protection in fabrication of integrated circuitsMOSEL VITELIC INC·Filed 2002·Granted May 20, 2003·51 cites·9 claims
- 0487US6562681B2Nonvolatile memories with floating gate spacers, and methods of fabricationMOSEL VITELIC INC·Filed 2001·Granted May 13, 2003·38 cites·32 claims
- 0583US7897659B2Water-based moldable modeling dough and method preparing thereforHUIZHOU SEASOAR ART SUPPLIES CO LTD·Filed 2009·Granted Mar 1, 2011·6 cites·14 claims
- 0683US6559055B2Dummy structures that protect circuit elements during polishingMOSEL VITELIC INC·Filed 2001·Granted May 6, 2003·26 cites·12 claims
- 0783US4905073AIntegrated circuit with improved tub tieAT & T BELL LAB·Filed 1989·Granted Feb 27, 1990·65 cites·13 claims
- 0882US4886765AMethod of making silicides by heating in oxygen to remove contaminationAMERICAN TELEPHONE & TELEGRAPH·Filed 1988·Granted Dec 12, 1989·41 cites·10 claims
- 0979US7910429B2Method of forming ONO-type sidewall with reduced bird's beakPROMOS TECHNOLOGIES INC·Filed 2004·Granted Mar 22, 2011·28 cites·21 claims
- 1078US6222764B1Erasable memory device and an associated method for erasing a memory cell thereinAGERE SYST GUARDIAN CORP·Filed 1999·Granted Apr 24, 2001·42 cites·29 claims
- 1176US5851870AMethod for making a capacitorLUCENT TECHNOLOGIES INC·Filed 1996·Granted Dec 22, 1998·31 cites·2 claims
- 1275US6570215B2Nonvolatile memories with floating gate spacers, and methods of fabricationMOSEL VITELIC INC·Filed 2002·Granted May 27, 2003·17 cites·18 claims
- 1374US6451660B1Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated waterAGERE SYST GUARDIAN CORP·Filed 2000·Granted Sep 17, 2002·18 cites·19 claims
- 1471US6815760B2Nonvolatile memory structures and fabrication methodsMOSEL VITELIC INC·Filed 2002·Granted Nov 9, 2004·10 cites·12 claims
- 1568US6168995B1Method of fabricating a split gate memory cellLUCENT TECHNOLOGIES INC·Filed 1999·Granted Jan 2, 2001·27 cites·8 claims
- 1666US6700143B2Dummy structures that protect circuit elements during polishingMOSEL VITELIC INC·Filed 2002·Granted Mar 2, 2004·9 cites·12 claims
- 1765US5102827AContact metallization of semiconductor integrated-circuit devicesAT & T BELL LAB·Filed 1991·Granted Apr 7, 1992·24 cites·12 claims
- 1864US6821847B2Nonvolatile memory structures and fabrication methodsMOSEL VITELIC INC·Filed 2001·Granted Nov 23, 2004·7 cites·35 claims
- 1963US6313500B1Split gate memory cellAGERE SYST GUARDIAN CORP·Filed 1999·Granted Nov 6, 2001·21 cites·16 claims
- 2060US6358807B1Bipolar semiconductor device and method of forming same having reduced transient enhanced diffusionAGERE SYST GUARDIAN CORP·Filed 2000·Granted Mar 19, 2002·9 cites·12 claims
- 2159US5312781AFlash EEPROM fabrication process that uses a selective wet chemical etchAT & T BELL LAB·Filed 1991·Granted May 17, 1994·29 cites·5 claims
- 2257US7511333B2Nonvolatile memory cell with multiple floating gates and a connection region in the channelPROMOS TECHNOLOGIES INC·Filed 2005·Granted Mar 31, 2009·1 cites·17 claims
- 2357US5045898ACMOS integrated circuit having improved isolationAT & T BELL LAB·Filed 1988·Granted Sep 3, 1991·22 cites·5 claims
- 2454US6962848B2Nonvolatile memory structures and fabrication methodsPROMOS TECHNOLOGIES INC·Filed 2003·Granted Nov 8, 2005·4 cites·10 claims
- 2547US2007090493A1Fabrication of nitrogen containing regions on silicon containing regions in integrated circuits, and integrated circuits obtained therebyPROMOS TECHNOLOGIES INC·Filed 2005·Application pending·0 cites
- 2645US2007138579A1Fabrication of nitrogen containing regions on silicon containing regions in integrated circuits, and integrated circuits obtained therebyDONG ZHONG·Filed 2007·Application pending·0 cites
- 2742US5843827AMethod of reducing dielectric damage from plasma etch chargingLUCENT TECHNOLOGIES INC·Filed 1996·Granted Dec 1, 1998·8 cites·6 claims
- 2839US5110756AMethod of semiconductor integrated circuit manufacturing which includes processing for reducing defect densityAT & T BELL LAB·Filed 1991·Granted May 5, 1992·10 cites·4 claims
- 2939US4420503ALow temperature elevated pressure glass flow/re-flow processRCA CORP·Filed 1982·Granted Dec 13, 1983·9 cites·9 claims
- 3036US6815302B2Method of making a bipolar transistor with an oxygen implanted emitter windowAGERE SYSTEMS INC·Filed 2001·Granted Nov 9, 2004·0 cites·20 claims
- 3134US6555871B1Flash memory device having a bipolar transistor formed integral thereto and a method of manufacture thereforAGERE SYSTEMS INC·Filed 2000·Granted Apr 29, 2003·0 cites·20 claims
- 3234US6537887B2Integrated circuit fabricationAGERE SYSTEMS INC·Filed 2000·Granted Mar 25, 2003·0 cites·13 claims
- 3333US6657281B1Bipolar transistor with a low K material in emitter base spacer regionsAGERE SYSTEMS INC·Filed 2000·Granted Dec 2, 2003·0 cites·13 claims
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