Inventor

RANDAZZO TODD A

US42 patents

⚠️ This page may combine multiple inventors who share the name “RANDAZZO TODD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANDAZZO TODD A

LSI LOGIC CORP

MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor

Simple bicmos process for creation of low trigger voltage SCR and zener diode pad protection

Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same

Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof

Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof

Linear capacitor and process for making same

Low voltage breakdown element for ESD trigger device

Analog capacitor in dual damascene process

NMOS electrostatic discharge protection device and method for CMOS integrated circuit

Semiconductor device with a pair of transistors having dual work function gate electrodes

Semiconductor device with a pair of transistors having dual work function gate electrodes

Voltage level shifter

CMOS varactor with constant dC/dV characteristic

Low voltage breakdown element for ESD trigger device

Level shifter reference generator

Swapped drain structures for electrostatic discharge protection

Formation of high-voltage and low-voltage devices on a semiconductor substrate

Method of forming analog capacitor dual damascene process

High speed input buffer circuit

Swapped drain structures for electrostatic discharge protection

High voltage tolerant thin film transistor

Analog capacitor in dual damascene process

Programmable transmit SCSI equalization

Control circuit for power

Method and apparatus for summing DC voltages

Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate

SYMBIOS INC

Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor

Simple BICMOS process for creation of low trigger voltage SCR and zener diode pad protection

Gate edge aligned EEPROM transistor

Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask

ATMEL CORP

Input/output transistors with optimized ESD protection

Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer

Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer

Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer

SYMBIOS LOGIC INC

Non-volatile memory which is programmable from a power source

Drain excluded EPROM cell

LSI LOGIC

Linear capacitor and process for making same

HONEYWELL INC

Radiation hardened field oxide for VLSI sub-micron MOS device

LSI CORP

Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers

FECHNER PAUL S

Neutron detector cell efficiency

RANDAZZO TODD A

Resistive voltage-down regulator for integrated circuit receivers

LARSEN BRADLEY J

Neutron detector with wafer-to-wafer bonding