Inventor · disambiguated record
Tobias Webel
Also filed as: WEBEL TOBIAS
38 granted patents·113 citations·filing 2004–2022
96Inventor score
Top patents by PatentIndex Score
38 records- 0192US11112846B2Predictive on-chip voltage simulation to detect near-future under voltage conditionsIBM·Filed 2018·Granted Sep 7, 2021·11 cites·15 claims
- 0291US10552250B2Proactive voltage droop reduction and/or mitigation in a processor coreIBM·Filed 2017·Granted Feb 4, 2020·6 cites·20 claims
- 0390US11029742B2Mitigating voltage droopIBM·Filed 2019·Granted Jun 8, 2021·12 cites·17 claims
- 0488US11275644B2Proactive voltage droop reduction and/or mitigation in a processor coreIBM·Filed 2019·Granted Mar 15, 2022·4 cites·20 claims
- 0585US7308592B2Redundant oscillator distribution in a multi-processor server systemIBM·Filed 2005·Granted Dec 11, 2007·16 cites·5 claims
- 0684US10365132B2Methods and systems for performing test and calibration of integrated sensorsIBM·Filed 2018·Granted Jul 30, 2019·2 cites·7 claims
- 0783US11989071B2Dynamic guard band with timing protection and with performance protectionIBM·Filed 2022·Granted May 21, 2024·1 cites·20 claims
- 0883US7966536B2Method and apparatus for automatic scan completion in the event of a system checkstopIBM·Filed 2008·Granted Jun 21, 2011·14 cites·20 claims
- 0980US9811150B2System and method for controlling idle state exits to manage DI/DT issuesIBM·Filed 2015·Granted Nov 7, 2017·3 cites·17 claims
- 1078US7487377B2Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computerIBM·Filed 2005·Granted Feb 3, 2009·7 cites·8 claims
- 1177US9874917B2Adaptive power capping in a chipIBM·Filed 2016·Granted Jan 23, 2018·2 cites·20 claims
- 1277US7865758B2Fault tolerant time synchronization mechanism in a scaleable multi-processor computerIBM·Filed 2008·Granted Jan 4, 2011·6 cites·8 claims
- 1374US7568138B2Method to prevent firmware defects from disturbing logic clocks to improve system reliabilityIBM·Filed 2006·Granted Jul 28, 2009·8 cites·6 claims
- 1473US8898503B2Low latency data transfer between clock domains operated in various synchronization modesIBM·Filed 2013·Granted Nov 25, 2014·3 cites·20 claims
- 1573US8868960B2Synchronous clock stop in a multi nodal computer systemBERGMANN TOBIAS·Filed 2011·Granted Oct 21, 2014·5 cites·12 claims
- 1672US11693728B2Proactive voltage droop reduction and/or mitigation in a processor coreIBM·Filed 2022·Granted Jul 4, 2023·0 cites·20 claims
- 1767US11817697B2Method to limit the time a semiconductor device operates above a maximum operating voltageIBM·Filed 2022·Granted Nov 14, 2023·0 cites·25 claims
- 1867US8499144B2Updating settings of a processor core concurrently to the operation of a multi core processor systemCONKLIN CHRISTOPHER R·Filed 2010·Granted Jul 30, 2013·4 cites·19 claims
- 1965US9575529B2Voltage droop reduction in a processorIBM·Filed 2015·Granted Feb 21, 2017·1 cites·17 claims
- 2064US7996715B2Multi nodal computer system and method for handling check stops in the multi nodal computer systemIBM·Filed 2008·Granted Aug 9, 2011·3 cites·7 claims
- 2160US7761726B2Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computerIBM·Filed 2008·Granted Jul 20, 2010·1 cites·7 claims
- 2258US10725517B2Distributed on chip network to mitigate voltage droopsIBM·Filed 2019·Granted Jul 28, 2020·0 cites·20 claims
- 2357US10598526B2Methods and systems for performing test and calibration of integrated sensorsIBM·Filed 2016·Granted Mar 24, 2020·0 cites·12 claims
- 2456US9342395B2Error checking using serial collection of error dataIBM·Filed 2014·Granted May 17, 2016·0 cites·18 claims
- 2555US10048734B2Adaptive power capping in a chipIBM·Filed 2017·Granted Aug 14, 2018·0 cites·1 claims
- 2655US9348686B2Error checking using serial collection of error dataIBM·Filed 2014·Granted May 24, 2016·0 cites·7 claims
- 2754US11586267B2Fine resolution on-chip voltage simulation to prevent under voltage conditionsIBM·Filed 2018·Granted Feb 21, 2023·0 cites·18 claims
- 2854US10481662B2Distributed on chip network to mitigate voltage droopsIBM·Filed 2016·Granted Nov 19, 2019·0 cites·20 claims
- 2954US7484118B2Multi nodal computer system and method for handling check stops in the multi nodal computer systemIBM·Filed 2004·Granted Jan 27, 2009·4 cites·3 claims
- 3053US11953982B2Dynamic guard band with timing protection and with performance protectionIBM·Filed 2022·Granted Apr 9, 2024·0 cites·20 claims
- 3153US11586265B2Voltage droop management through microarchitectural stall eventsIBM·Filed 2021·Granted Feb 21, 2023·0 cites·20 claims
- 3251US11789518B2Voltage overshoot managementIBM·Filed 2021·Granted Oct 17, 2023·0 cites·20 claims
- 3351US10955906B2Multi-layered processor throttle controllerIBM·Filed 2019·Granted Mar 23, 2021·0 cites·17 claims
- 3449US7788432B2System for performing a serial communication between a central control block and satellite componentsIBM·Filed 2008·Granted Aug 31, 2010·0 cites·16 claims
- 3548US11150716B2Dynamically optimizing margins of a processorIBM·Filed 2020·Granted Oct 19, 2021·0 cites·15 claims
- 3644US8140885B2Accounting for microprocessor resource consumptionBECKER DANIEL·Filed 2008·Granted Mar 20, 2012·0 cites·16 claims
- 3739US8479070B2Integrated circuit arrangement for test inputsBAUR ULRICH·Filed 2010·Granted Jul 2, 2013·0 cites·16 claims
- 3833US8090929B2Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modesMAGEE JEFFREY A·Filed 2008·Granted Jan 3, 2012·0 cites·20 claims
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