Inventor · disambiguated record
Sivananda K. Kanakasabapathy
Also filed as: KANAKASABAPATHY SIVANANDA · KANAKASABAPATHY SIVANANDA K · KANAKASABAPATHY SIVANANDA KRISHNAN · KANAKASABAPATHY SIVANANDHA K
204 granted patents·37 pending applications·1,799 citations·filing 2001–2025
99Inventor score
Files withIBM166LAM RES CORP17BASKER VEERARAGHAVAN S6KANAKASABAPATHY SIVANANDA K6KANAKASABAPATHY SIVANANDA5
Top patents by PatentIndex Score
241 records- 0199US9287135B1Sidewall image transfer process for fin patterningIBM·Filed 2015·Granted Mar 15, 2016·67 cites·20 claims
- 0299US8637384B2FinFET parasitic capacitance reduction using air gapANDO TAKASHI·Filed 2012·Granted Jan 28, 2014·374 cites·13 claims
- 0399US8637930B2FinFET parasitic capacitance reduction using air gapANDO TAKASHI·Filed 2011·Granted Jan 28, 2014·99 cites·14 claims
- 0498US12278125B2Integrated dry processes for patterning radiation photoresist patterningLAM RES CORP·Filed 2023·Granted Apr 15, 2025·8 cites·19 claims
- 0598US12183604B2Integrated dry processes for patterning radiation photoresist patterningLAM RES CORP·Filed 2023·Granted Dec 31, 2024·9 cites·37 claims
- 0698US9934970B1Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2017·Granted Apr 3, 2018·22 cites·13 claims
- 0798US9721848B1Cutting fins and gates in CMOS devicesIBM·Filed 2016·Granted Aug 1, 2017·32 cites·20 claims
- 0898US9589845B1Fin cut enabling single diffusion breaksIBM·Filed 2016·Granted Mar 7, 2017·42 cites·20 claims
- 0998US9543435B1Asymmetric multi-gate finFETIBM·Filed 2015·Granted Jan 10, 2017·23 cites·3 claims
- 1098US9472506B2Registration mark formation during sidewall image transfer processIBM·Filed 2015·Granted Oct 18, 2016·26 cites·7 claims
- 1198US9431399B1Method for forming merged contact for semiconductor deviceIBM·Filed 2015·Granted Aug 30, 2016·31 cites·20 claims
- 1298US8358012B2Metal semiconductor alloy structure for low contact resistanceIBM·Filed 2010·Granted Jan 22, 2013·53 cites·19 claims
- 1397US9991156B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2016·Granted Jun 5, 2018·15 cites·6 claims
- 1497US9773893B1Forming a sacrificial liner for dual channel devicesIBM·Filed 2016·Granted Sep 26, 2017·11 cites·20 claims
- 1597US9754798B1Hybridization fin reveal for uniform fin reveal depth across different fin pitchesIBM·Filed 2016·Granted Sep 5, 2017·17 cites·16 claims
- 1697US9741823B1Fin cut during replacement gate formationIBM·Filed 2016·Granted Aug 22, 2017·22 cites·10 claims
- 1797US8298943B1Self aligning via patterningARNOLD JOHN CHRISTOPHER·Filed 2011·Granted Oct 30, 2012·72 cites·9 claims
- 1896US12183589B2Tin oxide mandrels in patterningLAM RES CORP·Filed 2021·Granted Dec 31, 2024·3 cites·20 claims
- 1996US9881926B1Static random access memory (SRAM) density scaling by using middle of line (MOL) flowIBM·Filed 2016·Granted Jan 30, 2018·11 cites·12 claims
- 2096US9779944B1Method and structure for cut material selectionIBM·Filed 2016·Granted Oct 3, 2017·17 cites·19 claims
- 2196US9472447B1Confined eptaxial growth for continued pitch scalingIBM·Filed 2015·Granted Oct 18, 2016·14 cites·14 claims
- 2296US9209178B2finFET isolation by selective cyclic etchIBM·Filed 2013·Granted Dec 8, 2015·26 cites·11 claims
- 2396US8420464B2Spacer as hard mask scheme for in-situ doping in CMOS finFETsBASKER VEERARAGHAVAN S·Filed 2011·Granted Apr 16, 2013·33 cites·7 claims
- 2495US11355353B2Tin oxide mandrels in patterningLAM RES CORP·Filed 2019·Granted Jun 7, 2022·15 cites·15 claims
- 2595US10276452B1Low undercut N-P work function metal patterning in nanosheet replacement metal gate processIBM·Filed 2018·Granted Apr 30, 2019·13 cites·14 claims
- 2695US10083964B1Double diffusion break gate structure without vestigial antenna capacitanceIBM·Filed 2017·Granted Sep 25, 2018·10 cites·10 claims
- 2795US9728462B2Stable multiple threshold voltage devices on replacement metal gate CMOS devicesIBM·Filed 2015·Granted Aug 8, 2017·12 cites·9 claims
- 2895US9589958B1Pitch scalable active area patterning structure and process for multi-channel finFET technologiesIBM·Filed 2016·Granted Mar 7, 2017·12 cites·16 claims
- 2995US9305845B2Self-aligned quadruple patterning processIBM·Filed 2014·Granted Apr 5, 2016·17 cites·19 claims
- 3094US10050039B2Semiconductor structures with deep trench capacitor and methods of manufactureIBM·Filed 2017·Granted Aug 14, 2018·7 cites·18 claims
- 3194US9576096B2Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufactureIBM·Filed 2014·Granted Feb 21, 2017·12 cites·17 claims
- 3294US9064813B2Trench patterning with block first sidewall image transferIBM·Filed 2013·Granted Jun 23, 2015·14 cites·17 claims
- 3394US7642147B1Methods for removing sidewall spacersIBM·Filed 2008·Granted Jan 5, 2010·30 cites·7 claims
- 3493US10529569B2Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2018·Granted Jan 7, 2020·5 cites·11 claims
- 3593US10269806B2Semiconductor structures with deep trench capacitor and methods of manufactureIBM·Filed 2018·Granted Apr 23, 2019·5 cites·12 claims
- 3693US9627510B1Structure and method for replacement gate integration with self-aligned contactsIBM·Filed 2015·Granted Apr 18, 2017·8 cites·13 claims
- 3793US8455364B2Sidewall image transfer using the lithographic stack as the mandrelKANAKASABAPATHY SIVANANDA K·Filed 2009·Granted Jun 4, 2013·25 cites·20 claims
- 3893US7531367B2Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuitIBM·Filed 2006·Granted May 12, 2009·24 cites·1 claims
- 3992US11894462B2Forming a sacrificial liner for dual channel devicesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2021·Granted Feb 6, 2024·1 cites·20 claims
- 4092US10042968B2Semiconductor structures with deep trench capacitor and methods of manufactureIBM·Filed 2016·Granted Aug 7, 2018·5 cites·15 claims
- 4192US9881937B2Preventing strained fin relaxationIBM·Filed 2017·Granted Jan 30, 2018·6 cites·10 claims
- 4292US9607886B1Self aligned conductive lines with relaxed overlayIBM·Filed 2016·Granted Mar 28, 2017·6 cites·20 claims
- 4392US9331148B1FinFET device with channel strainIBM·Filed 2015·Granted May 3, 2016·6 cites·9 claims
- 4492US8735296B2Method of simultaneously forming multiple structures having different critical dimensions using sidewall transferJUNG RYAN O·Filed 2012·Granted May 27, 2014·18 cites·25 claims
- 4592US8518824B2Self aligning via patterningARNOLD JOHN CHRISTOPHER·Filed 2012·Granted Aug 27, 2013·13 cites·10 claims
- 4692US8486778B2Low resistance source and drain extensions for ETSOIHARAN BALASUBRAMANIAN S·Filed 2011·Granted Jul 16, 2013·13 cites·5 claims
- 4792US8421139B2Structure and method to integrate embedded DRAM with finfetKANAKASABAPATHY SIVANANDA·Filed 2010·Granted Apr 16, 2013·13 cites·12 claims
- 4891US11987876B2Chamfer-less via integration schemeLAM RES CORP·Filed 2019·Granted May 21, 2024·6 cites·27 claims
- 4991US10242981B2Fin cut during replacement gate formationIBM·Filed 2017·Granted Mar 26, 2019·5 cites·17 claims
- 5091US9704860B1Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxationIBM·Filed 2016·Granted Jul 11, 2017·5 cites·11 claims
Showing the top 50 of 241 patent records by PatentIndex Score.
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