Inventor · disambiguated record
Balaram Sinharoy
Also filed as: SINHAROY BALARAM
188 granted patents·13 pending applications·2,414 citations·filing 1999–2023
99Inventor score
Files withIBM149ARIMILLI RAVI K22ARIMILLI LAKSHMINARAYANA BABA3ARMSTRONG WILLIAM JOSEPH3BOHRER PATRICK JOSEPH3
Top patents by PatentIndex Score
201 records- 0196US6721874B1Method and system for dynamically shared completion table supporting multiple threads in a processing systemIBM·Filed 2000·Granted Apr 13, 2004·128 cites·23 claims
- 0295US10324856B2Address translation for sending real address to memory subsystem in effective address based load-store unitIBM·Filed 2017·Granted Jun 18, 2019·14 cites·7 claims
- 0395US10310988B2Address translation for sending real address to memory subsystem in effective address based load-store unitIBM·Filed 2017·Granted Jun 4, 2019·13 cites·13 claims
- 0495US8041928B2Information handling system with real and virtual load/store instruction issue queueIBM·Filed 2008·Granted Oct 18, 2011·46 cites·20 claims
- 0595US7913041B2Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hintIBM·Filed 2008·Granted Mar 22, 2011·38 cites·16 claims
- 0693US10963248B2Handling effective address synonyms in a load-store unit that operates without address translationIBM·Filed 2020·Granted Mar 30, 2021·3 cites·20 claims
- 0793US10417002B2Hazard detection of out-of-order execution of load and store instructions in processors without using real addressesIBM·Filed 2017·Granted Sep 17, 2019·9 cites·17 claims
- 0893US10394558B2Executing load-store operations without address translation hardware per load-store unit portIBM·Filed 2017·Granted Aug 27, 2019·8 cites·13 claims
- 0993US7779232B2Method and apparatus for dynamically managing instruction buffer depths for non-predicted branchesIBM·Filed 2007·Granted Aug 17, 2010·56 cites·20 claims
- 1093US7155600B2Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processorIBM·Filed 2003·Granted Dec 26, 2006·86 cites·16 claims
- 1192US10534616B2Load-hit-load detection in an out-of-order processorIBM·Filed 2017·Granted Jan 14, 2020·10 cites·19 claims
- 1292US7958327B2Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architectureIBM·Filed 2008·Granted Jun 7, 2011·29 cites·9 claims
- 1392US7051221B2Performance throttling for temperature reduction in a microprocessorIBM·Filed 2003·Granted May 23, 2006·85 cites·20 claims
- 1491US7941627B2Specialized memory move barrier operationsIBM·Filed 2008·Granted May 10, 2011·26 cites·12 claims
- 1590US10977047B2Hazard detection of out-of-order execution of load and store instructions in processors without using real addressesIBM·Filed 2019·Granted Apr 13, 2021·5 cites·17 claims
- 1690US8095758B2Fully asynchronous memory moverARIMILLI RAVI K·Filed 2008·Granted Jan 10, 2012·21 cites·20 claims
- 1790US7930504B2Handling of address conflicts during asynchronous memory move operationsIBM·Filed 2008·Granted Apr 19, 2011·22 cites·16 claims
- 1890US7707396B2Data processing system, processor and method of data processing having improved branch target address cacheIBM·Filed 2006·Granted Apr 27, 2010·30 cites·21 claims
- 1990US7634642B2Mechanism to save and restore cache and translation trace for fast context switchIBM·Filed 2006·Granted Dec 15, 2009·23 cites·21 claims
- 2090US7254678B2Enhanced STCX design to improve subsequent load efficiencyIBM·Filed 2005·Granted Aug 7, 2007·38 cites·20 claims
- 2188US10564976B2Scalable dependency matrix with multiple summary bits in an out-of-order processorIBM·Filed 2017·Granted Feb 18, 2020·5 cites·20 claims
- 2288US8161263B2Techniques for indirect data prefetchingARIMILLI RAVI K·Filed 2008·Granted Apr 17, 2012·19 cites·18 claims
- 2388US7844778B2Intelligent cache replacement mechanism with varying and adaptive temporal residency requirementsIBM·Filed 2006·Granted Nov 30, 2010·19 cites·22 claims
- 2488US7506139B2Method and apparatus for register renaming using multiple physical register files and avoiding associative searchIBM·Filed 2006·Granted Mar 17, 2009·17 cites·1 claims
- 2588US6823446B1Apparatus and method for performing branch predictions using dual branch history tables and for updating such branch history tablesIBM·Filed 2000·Granted Nov 23, 2004·55 cites·5 claims
- 2688US6449714B1Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction executionIBM·Filed 1999·Granted Sep 10, 2002·125 cites·20 claims
- 2787US8458709B2Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modesARMSTRONG WILLIAM JOSEPH·Filed 2009·Granted Jun 4, 2013·15 cites·12 claims
- 2887US8140764B2System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memorySHEN XIAOWEI·Filed 2011·Granted Mar 20, 2012·9 cites·3 claims
- 2987US7991981B2Completion of asynchronous memory move in the presence of a barrier operationIBM·Filed 2008·Granted Aug 2, 2011·17 cites·18 claims
- 3087US6877089B2Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing programIBM·Filed 2000·Granted Apr 5, 2005·51 cites·3 claims
- 3186US10481915B2Split store data queue design for an out-of-order processorIBM·Filed 2017·Granted Nov 19, 2019·4 cites·17 claims
- 3286US8327101B2Cache management during asynchronous memory move operationsARIMILLI RAVI K·Filed 2008·Granted Dec 4, 2012·16 cites·20 claims
- 3386US8245004B2Mechanisms for communicating with an asynchronous memory mover to perform AMM operationsARIMILLI RAVI K·Filed 2008·Granted Aug 14, 2012·15 cites·10 claims
- 3486US7921275B2Method for enabling direct prefetching of data during asychronous memory move operationIBM·Filed 2008·Granted Apr 5, 2011·16 cites·10 claims
- 3586US6247097B1Aligned instruction cache handling of instruction fetches across multiple predicted branch instructionsIBM·Filed 1999·Granted Jun 12, 2001·107 cites·24 claims
- 3685US11157280B2Dynamic fusion based on operand sizeIBM·Filed 2017·Granted Oct 26, 2021·4 cites·20 claims
- 3785US10628158B2Executing load-store operations without address translation hardware per load-store unit portIBM·Filed 2017·Granted Apr 21, 2020·3 cites·7 claims
- 3885US9489207B2Processor and method for partially flushing a dispatched instruction group including a mispredicted branchBURKY WILLIAM E·Filed 2009·Granted Nov 8, 2016·20 cites·16 claims
- 3985US7949859B2Mechanism for avoiding check stops in speculative accesses while operating in real modeIBM·Filed 2008·Granted May 24, 2011·13 cites·2 claims
- 4085US7937570B2Termination of in-flight asynchronous memory moveIBM·Filed 2008·Granted May 3, 2011·14 cites·14 claims
- 4185US7827388B2Apparatus for adjusting instruction thread priority in a multi-thread processorIBM·Filed 2008·Granted Nov 2, 2010·13 cites·13 claims
- 4285US7725682B2Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unitIBM·Filed 2006·Granted May 25, 2010·15 cites·20 claims
- 4385US6971000B1Use of software hint for branch prediction in the absence of hint bit in the branch instructionIBM·Filed 2000·Granted Nov 29, 2005·39 cites·16 claims
- 4484US11868773B2Inferring future value for speculative branch resolution in a microprocessorIBM·Filed 2022·Granted Jan 9, 2024·1 cites·20 claims
- 4584US8275963B2Asynchronous memory move across physical nodes with dual-sided communicationARIMILLI RAVI K·Filed 2008·Granted Sep 25, 2012·13 cites·12 claims
- 4684US8131976B2Tracking effective addresses in an out-of-order processorDOING RICHARD W·Filed 2009·Granted Mar 6, 2012·18 cites·22 claims
- 4784US7506132B2Validity of address ranges used in semi-synchronous memory copy operationsIBM·Filed 2005·Granted Mar 17, 2009·12 cites·6 claims
- 4884US7484062B2Cache injection semi-synchronous memory copy operationIBM·Filed 2005·Granted Jan 27, 2009·12 cites·3 claims
- 4984US6823447B2Software hint to improve the branch target prediction accuracyIBM·Filed 2001·Granted Nov 23, 2004·44 cites·15 claims
- 5084US6745323B1Global history vector recovery circuits and methods and systems using the sameIBM·Filed 2000·Granted Jun 1, 2004·37 cites·30 claims
Showing the top 50 of 201 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →