Inventor

DOCZY MARK L

US163 patents

Patents

50 patents

US7518196B2Apr 14, 2009

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

INTEL CORP72 citations99

US7126199B2Oct 24, 2006

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

INTEL CORP72 citations98

US7485503B2Feb 3, 2009

Dielectric interface for group III-V semiconductor device

INTEL CORP63 citations98

US7479421B2Jan 20, 2009

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

INTEL CORP105 citations98

US7390709B2Jun 24, 2008

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

INTEL CORP71 citations98

US7381608B2Jun 3, 2008

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

INTEL CORP85 citations98

US7329913B2Feb 12, 2008

Nonplanar transistors with metal gate electrodes

INTEL CORP114 citations98

US7279375B2Oct 9, 2007

Block contact architectures for nanoscale channel transistors

INTEL CORP93 citations98

US7226831B1Jun 5, 2007

Device with scavenging spacer layer

INTEL CORP60 citations98

US7220635B2May 22, 2007

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

INTEL CORP78 citations98

US7217611B2May 15, 2007

Methods for integrating replacement metal gate structures

INTEL CORP70 citations98

US7208361B2Apr 24, 2007

Replacement gate process for making a semiconductor device that includes a metal gate electrode

INTEL CORP128 citations98

US7157378B2Jan 2, 2007

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

INTEL CORP107 citations98

US7153734B2Dec 26, 2006

CMOS device with metal and silicide gate electrodes and a method for making it

INTEL CORP64 citations98

US7153784B2Dec 26, 2006

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

INTEL CORP86 citations98

US7148548B2Dec 12, 2006

Semiconductor device with a high-k gate dielectric and a metal gate electrode

INTEL CORP117 citations98

US7064066B1Jun 20, 2006

Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode

INTEL CORP65 citations98

US6696327B1Feb 24, 2004

Method for making a semiconductor device having a high-k gate dielectric

INTEL CORP85 citations98

US7074680B2Jul 11, 2006

Method for making a semiconductor device having a high-k gate dielectric

INTEL CORP64 citations97

US7893506B2Feb 22, 2011

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

INTEL CORP35 citations96

US7858481B2Dec 28, 2010

Method for fabricating transistor with thinned channel

INTEL CORP28 citations96

US7355281B2Apr 8, 2008

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

INTEL CORP47 citations96

US7323423B2Jan 29, 2008

Forming high-k dielectric layers on smooth substrates

INTEL CORP49 citations96

US7176090B2Feb 13, 2007

Method for making a semiconductor device that includes a metal gate electrode

INTEL CORP58 citations96

US7138323B2Nov 21, 2006

Planarizing a semiconductor structure to form replacement metal gates

INTEL CORP51 citations96

US7060568B2Jun 13, 2006

Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit

INTEL CORP53 citations96

US6716707B1Apr 6, 2004

Method for making a semiconductor device having a high-k gate dielectric

INTEL CORP52 citations96

US6709911B1Mar 23, 2004

Method for making a semiconductor device having a high-k gate dielectric

INTEL CORP64 citations96

US8368135B2Feb 5, 2013

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

INTEL CORP8 citations93

US7989280B2Aug 2, 2011

Dielectric interface for group III-V semiconductor device

INTEL CORP20 citations93

US7902058B2Mar 8, 2011

Inducing strain in the channels of metal gate transistors

INTEL CORP30 citations93

US7825481B2Nov 2, 2010

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

INTEL CORP12 citations93

US7718479B2May 18, 2010

Forming integrated circuits with replacement metal gate electrodes

INTEL CORP15 citations93

US7704833B2Apr 27, 2010

Method of forming abrupt source drain metal gate transistors

INTEL CORP22 citations93

US7429747B2Sep 30, 2008

Sb-based CMOS devices

INTEL CORP39 citations93

US7425500B2Sep 16, 2008

Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors

INTEL CORP45 citations93

US7384880B2Jun 10, 2008

Method for making a semiconductor device having a high-k gate dielectric

INTEL CORP29 citations93

US7355254B2Apr 8, 2008

Pinning layer for low resistivity N-type source drain ohmic contacts

INTEL CORP50 citations93

US7317231B2Jan 8, 2008

Method for making a semiconductor device having a high-K gate dielectric and a titanium carbide gate electrode

INTEL CORP35 citations93

US7183184B2Feb 27, 2007

Method for making a semiconductor device that includes a metal gate electrode

INTEL CORP54 citations93

US7160767B2Jan 9, 2007

Method for making a semiconductor device that includes a metal gate electrode

INTEL CORP54 citations93

US7148099B2Dec 12, 2006

Reducing the dielectric constant of a portion of a gate dielectric

INTEL CORP20 citations93

US7144783B2Dec 5, 2006

Reducing gate dielectric material to form a metal gate electrode extension

INTEL CORP37 citations93

US7078750B2Jul 18, 2006

Method of fabricating a robust gate dielectric using a replacement gate flow

INTEL CORP16 citations93

US6939815B2Sep 6, 2005

Method for making a semiconductor device having a high-k gate dielectric

INTEL CORP20 citations93

US6893927B1May 17, 2005

Method for making a semiconductor device with a metal gate electrode

INTEL CORP38 citations93

US6887800B1May 3, 2005

Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction

INTEL CORP23 citations93

Showing the top 50 of 163 patents by PatentIndex Score.

DOCZY MARK L

Patents

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Multilayer metal gate electrode

Nonplanar transistors with metal gate electrodes

Block contact architectures for nanoscale channel transistors

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

Nonplanar transistors with metal gate electrodes

Block contact architectures for nanoscale channel transistors

Device with scavenging spacer layer

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Methods for integrating replacement metal gate structures

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Method for fabricating transistor with thinned channel

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Forming high-k dielectric layers on smooth substrates

Method for making a semiconductor device that includes a metal gate electrode

Planarizing a semiconductor structure to form replacement metal gates

Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Dielectric interface for group III-V semiconductor device

Inducing strain in the channels of metal gate transistors

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Forming integrated circuits with replacement metal gate electrodes

Method of forming abrupt source drain metal gate transistors

Sb-based CMOS devices

Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors

Method for making a semiconductor device having a high-k gate dielectric

Pinning layer for low resistivity N-type source drain ohmic contacts

Method for making a semiconductor device having a high-K gate dielectric and a titanium carbide gate electrode

Method for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device that includes a metal gate electrode

Reducing the dielectric constant of a portion of a gate dielectric

Reducing gate dielectric material to form a metal gate electrode extension

Method of fabricating a robust gate dielectric using a replacement gate flow

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device with a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction