Inventor · disambiguated record
Amit Merchant
Also filed as: MERCHANT AMIT · MERCHANT AMIT A
38 granted patents·2,086 citations·filing 1991–2020
99Inventor score
Top patents by PatentIndex Score
38 records- 0197US6385715B1Multi-threading for a processor utilizing a replay queueINTEL CORP·Filed 2001·Granted May 7, 2002·152 cites·29 claims
- 0297US5237535AMethod of repairing overerased cells in a flash memoryINTEL CORP·Filed 1991·Granted Aug 17, 1993·178 cites·38 claims
- 0394US5327383AMethod and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancyINTEL CORP·Filed 1992·Granted Jul 5, 1994·114 cites·34 claims
- 0493US5377147AMethod and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancyINTEL CORP·Filed 1993·Granted Dec 27, 1994·90 cites·3 claims
- 0593US5347489AMethod and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancyINTEL CORP·Filed 1992·Granted Sep 13, 1994·93 cites·3 claims
- 0692US7039794B2Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processorINTEL CORP·Filed 2002·Granted May 2, 2006·64 cites·32 claims
- 0792US6792446B2Storing of instructions relating to a stalled threadINTEL CORP·Filed 2002·Granted Sep 14, 2004·60 cites·12 claims
- 0891US5893151AMethod and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requestsINTEL CORP·Filed 1997·Granted Apr 6, 1999·124 cites·3 claims
- 0990US6496925B1Method and apparatus for processing an event occurrence within a multithreaded processorINTEL CORP·Filed 1999·Granted Dec 17, 2002·117 cites·32 claims
- 1089US6889319B1Method and apparatus for entering and exiting multiple threads within a multithreaded processorINTEL CORP·Filed 1999·Granted May 3, 2005·133 cites·33 claims
- 1188US6785803B1Processor including replay queue to break livelocksINTEL CORP·Filed 2000·Granted Aug 31, 2004·55 cites·20 claims
- 1288US6772322B1Method and apparatus to monitor the performance of a processorINTEL CORP·Filed 2000·Granted Aug 3, 2004·74 cites·24 claims
- 1382US8898434B2Optimizing system throughput by automatically altering thread co-execution based on operating system directivesMERCHANT AMIT·Filed 2011·Granted Nov 25, 2014·8 cites·14 claims
- 1481US5875467AMethod and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requestsINTEL CORP·Filed 1997·Granted Feb 23, 1999·61 cites·3 claims
- 1580US7219349B2Multi-threading techniques for a processor utilizing a replay queueINTEL CORP·Filed 2004·Granted May 15, 2007·20 cites·12 claims
- 1679US8898435B2Optimizing system throughput by automatically altering thread co-execution based on operating system directivesIBM·Filed 2013·Granted Nov 25, 2014·4 cites·7 claims
- 1779US5890200AMethod and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requestsINTEL CORP·Filed 1997·Granted Mar 30, 1999·54 cites·4 claims
- 1878US7353370B2Method and apparatus for processing an event occurrence within a multithreaded processorINTEL CORP·Filed 2005·Granted Apr 1, 2008·6 cites·24 claims
- 1977US6163838AComputer processor with a replay systemINTEL CORP·Filed 1998·Granted Dec 19, 2000·74 cites·26 claims
- 2075US6334182B2Scheduling operations using a dependency matrixINTEL CORP·Filed 1998·Granted Dec 25, 2001·69 cites·15 claims
- 2175US5737759AMethod and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requestsINTEL CORP·Filed 1997·Granted Apr 7, 1998·44 cites·10 claims
- 2271US5572703AMethod and apparatus for snoop stretching using signals that convey snoop resultsINTEL CORP·Filed 1994·Granted Nov 5, 1996·47 cites·40 claims
- 2370US6094717AComputer processor with a replay system having a plurality of checkersINTEL CORP·Filed 1998·Granted Jul 25, 2000·55 cites·30 claims
- 2470US5778438AMethod and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requestsINTEL CORP·Filed 1995·Granted Jul 7, 1998·37 cites·1 claims
- 2570US5682516AComputer system that maintains system wide cache coherency during deferred communication transactionsINTEL CORP·Filed 1994·Granted Oct 28, 1997·58 cites·38 claims
- 2669US7366879B2Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statusesINTEL CORP·Filed 2004·Granted Apr 29, 2008·12 cites·32 claims
- 2768US7200737B1Processor with a replay system that includes a replay queue for improved throughputINTEL CORP·Filed 1999·Granted Apr 3, 2007·49 cites·26 claims
- 2867US5737758AMethod and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requestsINTEL CORP·Filed 1997·Granted Apr 7, 1998·32 cites·5 claims
- 2967US5572702AMethod and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistencyINTEL CORP·Filed 1994·Granted Nov 5, 1996·40 cites·30 claims
- 3065US6212626B1Computer processor having a checkerINTEL CORP·Filed 1998·Granted Apr 3, 2001·42 cites·25 claims
- 3163US7089409B2Interface to a memory system for a processor having a replay systemINTEL CORP·Filed 2003·Granted Aug 8, 2006·7 cites·25 claims
- 3263US6665792B1Interface to a memory system for a processor having a replay systemINTEL CORP·Filed 1999·Granted Dec 16, 2003·35 cites·21 claims
- 3362US5797026AMethod and apparatus for self-snooping a bus during a boundary transactionINTEL CORP·Filed 1997·Granted Aug 18, 1998·41 cites·30 claims
- 3458US9178770B2Auto incorporation of new components into a hierarchical networkIBM·Filed 2013·Granted Nov 3, 2015·1 cites·13 claims
- 3557US5537357AMethod for preconditioning a nonvolatile memory arrayINTEL CORP·Filed 1994·Granted Jul 16, 1996·17 cites·8 claims
- 3649US5909699AMethod and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistencyINTEL CORP·Filed 1996·Granted Jun 1, 1999·19 cites·24 claims
- 3747US9178939B2Auto incorporation of new components into a hierarchical networkIBM·Filed 2014·Granted Nov 3, 2015·0 cites·7 claims
- 3846US11307902B1Preventing deployment failures of information technology workloadsKYNDRYL INC·Filed 2020·Granted Apr 19, 2022·0 cites·21 claims
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