Inventor · disambiguated record
Chine-Gie Lou
Also filed as: LOU CHINE-GIE
73 granted patents·2 pending applications·2,331 citations·filing 1995–2008
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG28WORLDWIDE SEMICONDUCTOR MFG20WORLDWIDE SEMICONDUCTOR MANUFA12IND TECH RES INST10TAIWAN SEMICONDUCTOR MFG CORP2
Top patents by PatentIndex Score
75 records- 0199US6403486B1Method for forming a shallow trench isolationTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·254 cites·27 claims
- 0295US6274497B1Copper damascene manufacturing processTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Aug 14, 2001·108 cites·17 claims
- 0394US7371663B2Three dimensional IC device and alignment methods of IC device substratesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted May 13, 2008·22 cites·8 claims
- 0494US6492270B1Method for forming copper dual damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 10, 2002·77 cites·33 claims
- 0594US6204141B1Method of manufacturing a deep trench capacitorTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Mar 20, 2001·65 cites·17 claims
- 0694US5759906APlanarization method for intermetal dielectrics between multilevel interconnections on integrated circuitsIND TECH RES INST·Filed 1997·Granted Jun 2, 1998·163 cites·19 claims
- 0793US6174769B1Method for manufacturing stacked capacitorWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Jan 16, 2001·111 cites·19 claims
- 0890US6468858B1Method of forming a metal insulator metal capacitor structureTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·51 cites·24 claims
- 0989US6291333B1Method of fabricating dual damascene structureTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 18, 2001·55 cites·15 claims
- 1087US5872045AMethod for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolationIND TECH RES INST·Filed 1997·Granted Feb 16, 1999·96 cites·21 claims
- 1185US5597754AIncreased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal processIND TECH RES INST·Filed 1995·Granted Jan 28, 1997·88 cites·20 claims
- 1282US7781892B2Interconnect structure and method of fabricating sameTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Aug 24, 2010·12 cites·20 claims
- 1382US6265307B1Fabrication method for a dual damascene structureTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Jul 24, 2001·28 cites·19 claims
- 1482US6100129AMethod for making fin-trench structured DRAM capacitorWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1998·Granted Aug 8, 2000·49 cites·8 claims
- 1581US5827766AMethod for fabricating cylindrical capacitor for a memory cellIND TECH RES INST·Filed 1997·Granted Oct 27, 1998·49 cites·10 claims
- 1681US5618747AProcess for producing a stacked capacitor having polysilicon with optimum hemispherical grainsIND TECH RES INST·Filed 1996·Granted Apr 8, 1997·49 cites·12 claims
- 1780US6432794B1Process for fabricating capacitorWORLDWIDE SEMICONDUCTOR MFG·Filed 2000·Granted Aug 13, 2002·23 cites·14 claims
- 1879US6451650B1Low thermal budget method for forming MIM capacitorTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 17, 2002·26 cites·17 claims
- 1979US5916823AMethod for making dual damascene contactWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1998·Granted Jun 29, 1999·56 cites·11 claims
- 2078US6856156B2Automatically adjustable wafer probe cardTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Feb 15, 2005·25 cites·17 claims
- 2177US6440847B1Method for forming a via and interconnect in dual damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Aug 27, 2002·24 cites·36 claims
- 2275US6159793AStructure and fabricating method of stacked capacitorWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Dec 12, 2000·45 cites·16 claims
- 2375US6110826ADual damascene process using selective W CVDIND TECH RES INST·Filed 1998·Granted Aug 29, 2000·49 cites·33 claims
- 2475US6074942AMethod for forming a dual damascene contact and interconnectWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1998·Granted Jun 13, 2000·45 cites·13 claims
- 2574US6784098B1Method for forming salicide processTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Aug 31, 2004·20 cites·11 claims
- 2674US6417066B1Method of forming a DRAM capacitor structure including increasing the surface area using a discrete silicon maskTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·20 cites·26 claims
- 2774US6372653B1Method of forming dual damascene structureTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Apr 16, 2002·23 cites·20 claims
- 2873US6251735B1Method of forming shallow trench isolation structureTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 26, 2001·42 cites·11 claims
- 2973US6184159B1Interlayer dielectric planarization processTAIWAN SEMICONDUCTOR MFG CORP·Filed 1998·Granted Feb 6, 2001·49 cites·2 claims
- 3072US5932487AMethod for forming a planar intermetal dielectric layerWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1998·Granted Aug 3, 1999·38 cites·16 claims
- 3171US8232659B2Three dimensional IC device and alignment methods of IC device substratesCHEN HSUEH-CHUNG·Filed 2008·Granted Jul 31, 2012·4 cites·9 claims
- 3270US6239017B1Dual damascene CMP process with BPSG reflowed contact holeIND TECH RES INST·Filed 1998·Granted May 29, 2001·37 cites·20 claims
- 3370US6235579B1Method for manufacturing stacked capacitorTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 22, 2001·38 cites·23 claims
- 3468US6323112B1Method of fabricating integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Nov 27, 2001·14 cites·22 claims
- 3567US6090679AMethod for forming a crown capacitorWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1998·Granted Jul 18, 2000·26 cites·15 claims
- 3666US6093590AMethod of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constantWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1999·Granted Jul 25, 2000·31 cites·14 claims
- 3763US6271099B1Method for forming a capacitor of a DRAM cellWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Aug 7, 2001·21 cites·20 claims
- 3863US6187661B1Method for fabricating metal interconnect structureWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Feb 13, 2001·28 cites·15 claims
- 3962US6211569B1Interconnection lines for improving thermal conductivity in integrated circuits and method for fabricating the sameWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Apr 3, 2001·27 cites·10 claims
- 4058US6376326B1Method of manufacturing DRAM capacitorTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Apr 23, 2002·8 cites·26 claims
- 4158US6358845B1Method for forming inter metal dielectricTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Mar 19, 2002·8 cites·19 claims
- 4257US6200881B1Method of forming a shallow trench isolationWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Mar 13, 2001·22 cites·20 claims
- 4357US6187486B1Method of multi-exposure for improving photolithography resolutionWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Feb 13, 2001·18 cites·6 claims
- 4456US6271083B1Method of forming a dram crown capacitorWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Aug 7, 2001·21 cites·17 claims
- 4556US6171928B1Method of fabricating shallow trench insolationWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Jan 9, 2001·20 cites·18 claims
- 4655US6146968AMethod for forming a crown capacitorTAIWAN SEMICONDUCTOR MFG CORP·Filed 1998·Granted Nov 14, 2000·16 cites·6 claims
- 4751US6277732B1Method of planarizing inter-metal dielectric layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 21, 2001·17 cites·5 claims
- 4851US6271116B1Method of fabricating interconnectsTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Aug 7, 2001·4 cites·18 claims
- 4951US6143605AMethod for making a DRAM capacitor using a double layer of insitu doped polysilicon and undoped amorphous polysilicon with HSG polysiliconWORLDWIDE SEMICONDUCTOR MFG·Filed 1998·Granted Nov 7, 2000·12 cites·19 claims
- 5051US6117748ADishing free process for shallow trench isolationWORLDWIDE SEMICONDUCTOR MANUFA·Filed 1998·Granted Sep 12, 2000·17 cites·14 claims
Showing the top 50 of 75 patent records by PatentIndex Score.
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